usb_fpga.tan.qmsg

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

{ "Info" "ITDB_FULL_TCO_RESULT" "gclk RDY1_SLWR fifordaddr\[5\] 15.702 ns register " "Info: tco from clock \"gclk\" to destination pin \"RDY1_SLWR\" through register \"fifordaddr\[5\]\" is 15.702 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gclk source 2.963 ns + Longest register " "Info: + Longest clock path from clock \"gclk\" to source register is 2.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns gclk 1 CLK PIN_28 184 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 184; CLK Node = 'gclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { gclk } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.711 ns) 2.963 ns fifordaddr\[5\] 2 REG LC_X20_Y15_N6 10 " "Info: 2: + IC(0.783 ns) + CELL(0.711 ns) = 2.963 ns; Loc. = LC_X20_Y15_N6; Fanout = 10; REG Node = 'fifordaddr\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.494 ns" { gclk fifordaddr[5] } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.57 % ) " "Info: Total cell delay = 2.180 ns ( 73.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 26.43 % ) " "Info: Total interconnect delay = 0.783 ns ( 26.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.963 ns" { gclk fifordaddr[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.963 ns" { gclk gclk~out0 fifordaddr[5] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.515 ns + Longest register pin " "Info: + Longest register to pin delay is 12.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifordaddr\[5\] 1 REG LC_X20_Y15_N6 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y15_N6; Fanout = 10; REG Node = 'fifordaddr\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { fifordaddr[5] } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.061 ns) + CELL(0.575 ns) 2.636 ns LessThan~430COUT1_463 2 COMB LC_X21_Y14_N5 1 " "Info: 2: + IC(2.061 ns) + CELL(0.575 ns) = 2.636 ns; Loc. = LC_X21_Y14_N5; Fanout = 1; COMB Node = 'LessThan~430COUT1_463'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.636 ns" { fifordaddr[5] LessThan~430COUT1_463 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.716 ns LessThan~425COUT1_464 3 COMB LC_X21_Y14_N6 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 2.716 ns; Loc. = LC_X21_Y14_N6; Fanout = 1; COMB Node = 'LessThan~425COUT1_464'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "0.080 ns" { LessThan~430COUT1_463 LessThan~425COUT1_464 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.796 ns LessThan~420COUT1_465 4 COMB LC_X21_Y14_N7 1 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.796 ns; Loc. = LC_X21_Y14_N7; Fanout = 1; COMB Node = 'LessThan~420COUT1_465'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "0.080 ns" { LessThan~425COUT1_464 LessThan~420COUT1_465 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 2.876 ns LessThan~415COUT1_466 5 COMB LC_X21_Y14_N8 1 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 2.876 ns; Loc. = LC_X21_Y14_N8; Fanout = 1; COMB Node = 'LessThan~415COUT1_466'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "0.080 ns" { LessThan~420COUT1_465 LessThan~415COUT1_466 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 3.484 ns LessThan~407 6 COMB LC_X21_Y14_N9 1 " "Info: 6: + IC(0.000 ns) + CELL(0.608 ns) = 3.484 ns; Loc. = LC_X21_Y14_N9; Fanout = 1; COMB Node = 'LessThan~407'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "0.608 ns" { LessThan~415COUT1_466 LessThan~407 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.574 ns) + CELL(0.442 ns) 5.500 ns fifoff~89 7 COMB LC_X20_Y13_N7 1 " "Info: 7: + IC(1.574 ns) + CELL(0.442 ns) = 5.500 ns; Loc. = LC_X20_Y13_N7; Fanout = 1; COMB Node = 'fifoff~89'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.016 ns" { LessThan~407 fifoff~89 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.292 ns) 6.242 ns fifoff~92 8 COMB LC_X20_Y13_N8 1 " "Info: 8: + IC(0.450 ns) + CELL(0.292 ns) = 6.242 ns; Loc. = LC_X20_Y13_N8; Fanout = 1; COMB Node = 'fifoff~92'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "0.742 ns" { fifoff~89 fifoff~92 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.208 ns) + CELL(0.114 ns) 7.564 ns fifoff~93 9 COMB LC_X19_Y15_N6 1 " "Info: 9: + IC(1.208 ns) + CELL(0.114 ns) = 7.564 ns; Loc. = LC_X19_Y15_N6; Fanout = 1; COMB Node = 'fifoff~93'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.322 ns" { fifoff~92 fifoff~93 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.827 ns) + CELL(2.124 ns) 12.515 ns RDY1_SLWR 10 PIN PIN_178 0 " "Info: 10: + IC(2.827 ns) + CELL(2.124 ns) = 12.515 ns; Loc. = PIN_178; Fanout = 0; PIN Node = 'RDY1_SLWR'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "4.951 ns" { fifoff~93 RDY1_SLWR } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.395 ns ( 35.12 % ) " "Info: Total cell delay = 4.395 ns ( 35.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.120 ns ( 64.88 % ) " "Info: Total interconnect delay = 8.120 ns ( 64.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "12.515 ns" { fifordaddr[5] LessThan~430COUT1_463 LessThan~425COUT1_464 LessThan~420COUT1_465 LessThan~415COUT1_466 LessThan~407 fifoff~89 fifoff~92 fifoff~93 RDY1_SLWR } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.515 ns" { fifordaddr[5] LessThan~430COUT1_463 LessThan~425COUT1_464 LessThan~420COUT1_465 LessThan~415COUT1_466 LessThan~407 fifoff~89 fifoff~92 fifoff~93 RDY1_SLWR } { 0.000ns 2.061ns 0.000ns 0.000ns 0.000ns 0.000ns 1.574ns 0.450ns 1.208ns 2.827ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.608ns 0.442ns 0.292ns 0.114ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.963 ns" { gclk fifordaddr[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.963 ns" { gclk gclk~out0 fifordaddr[5] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "12.515 ns" { fifordaddr[5] LessThan~430COUT1_463 LessThan~425COUT1_464 LessThan~420COUT1_465 LessThan~415COUT1_466 LessThan~407 fifoff~89 fifoff~92 fifoff~93 RDY1_SLWR } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "12.515 ns" { fifordaddr[5] LessThan~430COUT1_463 LessThan~425COUT1_464 LessThan~420COUT1_465 LessThan~415COUT1_466 LessThan~407 fifoff~89 fifoff~92 fifoff~93 RDY1_SLWR } { 0.000ns 2.061ns 0.000ns 0.000ns 0.000ns 0.000ns 1.574ns 0.450ns 1.208ns 2.827ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.608ns 0.442ns 0.292ns 0.114ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "KEY1 LED1 11.567 ns Longest " "Info: Longest tpd from source pin \"KEY1\" to destination pin \"LED1\" is 11.567 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KEY1 1 PIN PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 1; PIN Node = 'KEY1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { KEY1 } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.974 ns) + CELL(2.124 ns) 11.567 ns LED1 2 PIN PIN_141 0 " "Info: 2: + IC(7.974 ns) + CELL(2.124 ns) = 11.567 ns; Loc. = PIN_141; Fanout = 0; PIN Node = 'LED1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "10.098 ns" { KEY1 LED1 } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.593 ns ( 31.06 % ) " "Info: Total cell delay = 3.593 ns ( 31.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.974 ns ( 68.94 % ) " "Info: Total interconnect delay = 7.974 ns ( 68.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "11.567 ns" { KEY1 LED1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.567 ns" { KEY1 KEY1~out0 LED1 } { 0.000ns 0.000ns 7.974ns } { 0.000ns 1.469ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "FX2FD\[7\]~reg0 RESETFPGA gclk -0.704 ns register " "Info: th for register \"FX2FD\[7\]~reg0\" (data pin = \"RESETFPGA\", clock pin = \"gclk\") is -0.704 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gclk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"gclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns gclk 1 CLK PIN_28 184 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 184; CLK Node = 'gclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { gclk } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns FX2FD\[7\]~reg0 2 REG LC_X8_Y19_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X8_Y19_N2; Fanout = 1; REG Node = 'FX2FD\[7\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.485 ns" { gclk FX2FD[7]~reg0 } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.954 ns" { gclk FX2FD[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.954 ns" { gclk gclk~out0 FX2FD[7]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.673 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns RESETFPGA 1 PIN PIN_153 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 44; PIN Node = 'RESETFPGA'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { RESETFPGA } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.337 ns) + CELL(0.867 ns) 3.673 ns FX2FD\[7\]~reg0 2 REG LC_X8_Y19_N2 1 " "Info: 2: + IC(1.337 ns) + CELL(0.867 ns) = 3.673 ns; Loc. = LC_X8_Y19_N2; Fanout = 1; REG Node = 'FX2FD\[7\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.204 ns" { RESETFPGA FX2FD[7]~reg0 } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 63.60 % ) " "Info: Total cell delay = 2.336 ns ( 63.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.337 ns ( 36.40 % ) " "Info: Total interconnect delay = 1.337 ns ( 36.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "3.673 ns" { RESETFPGA FX2FD[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.673 ns" { RESETFPGA RESETFPGA~out0 FX2FD[7]~reg0 } { 0.000ns 0.000ns 1.337ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.954 ns" { gclk FX2FD[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.954 ns" { gclk gclk~out0 FX2FD[7]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "3.673 ns" { RESETFPGA FX2FD[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.673 ns" { RESETFPGA RESETFPGA~out0 FX2FD[7]~reg0 } { 0.000ns 0.000ns 1.337ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}