usb_fpga.tan.qmsg

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "gclk " "Info: Assuming node \"gclk\" is an undefined clock" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 14 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "gclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "gclk register fifordaddr\[2\] memory altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|ram_block1a0~portb_address_reg3 121.92 MHz 8.202 ns Internal " "Info: Clock \"gclk\" has Internal fmax of 121.92 MHz between source register \"fifordaddr\[2\]\" and destination memory \"altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|ram_block1a0~portb_address_reg3\" (period= 8.202 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.891 ns + Longest register memory " "Info: + Longest register to memory delay is 7.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifordaddr\[2\] 1 REG LC_X19_Y15_N3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y15_N3; Fanout = 10; REG Node = 'fifordaddr\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { fifordaddr[2] } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.064 ns) + CELL(0.575 ns) 2.639 ns add~1113COUT1_1146 2 COMB LC_X21_Y15_N2 2 " "Info: 2: + IC(2.064 ns) + CELL(0.575 ns) = 2.639 ns; Loc. = LC_X21_Y15_N2; Fanout = 2; COMB Node = 'add~1113COUT1_1146'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.639 ns" { fifordaddr[2] add~1113COUT1_1146 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 3.247 ns add~1105 3 COMB LC_X21_Y15_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 3.247 ns; Loc. = LC_X21_Y15_N3; Fanout = 2; COMB Node = 'add~1105'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "0.608 ns" { add~1113COUT1_1146 add~1105 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.590 ns) 4.556 ns add~1110 4 COMB LC_X20_Y15_N7 4 " "Info: 4: + IC(0.719 ns) + CELL(0.590 ns) = 4.556 ns; Loc. = LC_X20_Y15_N7; Fanout = 4; COMB Node = 'add~1110'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.309 ns" { add~1105 add~1110 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.005 ns) + CELL(0.330 ns) 7.891 ns altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|ram_block1a0~portb_address_reg3 5 MEM M4K_X17_Y14 4 " "Info: 5: + IC(3.005 ns) + CELL(0.330 ns) = 7.891 ns; Loc. = M4K_X17_Y14; Fanout = 4; MEM Node = 'altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|ram_block1a0~portb_address_reg3'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "3.335 ns" { add~1110 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_lk81.tdf" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/altsyncram_lk81.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.103 ns ( 26.65 % ) " "Info: Total cell delay = 2.103 ns ( 26.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.788 ns ( 73.35 % ) " "Info: Total interconnect delay = 5.788 ns ( 73.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "7.891 ns" { fifordaddr[2] add~1113COUT1_1146 add~1105 add~1110 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.891 ns" { fifordaddr[2] add~1113COUT1_1146 add~1105 add~1110 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 2.064ns 0.000ns 0.719ns 3.005ns } { 0.000ns 0.575ns 0.608ns 0.590ns 0.330ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns - Smallest " "Info: - Smallest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gclk destination 2.969 ns + Shortest memory " "Info: + Shortest clock path from clock \"gclk\" to destination memory is 2.969 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns gclk 1 CLK PIN_28 184 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 184; CLK Node = 'gclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { gclk } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.718 ns) 2.969 ns altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|ram_block1a0~portb_address_reg3 2 MEM M4K_X17_Y14 4 " "Info: 2: + IC(0.782 ns) + CELL(0.718 ns) = 2.969 ns; Loc. = M4K_X17_Y14; Fanout = 4; MEM Node = 'altsyncram:fifomemory_rtl_0\|altsyncram_lk81:auto_generated\|ram_block1a0~portb_address_reg3'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.500 ns" { gclk altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } "" } } { "db/altsyncram_lk81.tdf" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/altsyncram_lk81.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.187 ns ( 73.66 % ) " "Info: Total cell delay = 2.187 ns ( 73.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.34 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.969 ns" { gclk altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.969 ns" { gclk gclk~out0 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.718ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gclk source 2.963 ns - Longest register " "Info: - Longest clock path from clock \"gclk\" to source register is 2.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns gclk 1 CLK PIN_28 184 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 184; CLK Node = 'gclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { gclk } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.711 ns) 2.963 ns fifordaddr\[2\] 2 REG LC_X19_Y15_N3 10 " "Info: 2: + IC(0.783 ns) + CELL(0.711 ns) = 2.963 ns; Loc. = LC_X19_Y15_N3; Fanout = 10; REG Node = 'fifordaddr\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.494 ns" { gclk fifordaddr[2] } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.57 % ) " "Info: Total cell delay = 2.180 ns ( 73.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 26.43 % ) " "Info: Total interconnect delay = 0.783 ns ( 26.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.963 ns" { gclk fifordaddr[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.963 ns" { gclk gclk~out0 fifordaddr[2] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.969 ns" { gclk altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.969 ns" { gclk gclk~out0 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.718ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.963 ns" { gclk fifordaddr[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.963 ns" { gclk gclk~out0 fifordaddr[2] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_lk81.tdf" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/altsyncram_lk81.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "7.891 ns" { fifordaddr[2] add~1113COUT1_1146 add~1105 add~1110 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.891 ns" { fifordaddr[2] add~1113COUT1_1146 add~1105 add~1110 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 2.064ns 0.000ns 0.719ns 3.005ns } { 0.000ns 0.575ns 0.608ns 0.590ns 0.330ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.969 ns" { gclk altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.969 ns" { gclk gclk~out0 altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|ram_block1a0~portb_address_reg3 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.718ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.963 ns" { gclk fifordaddr[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.963 ns" { gclk gclk~out0 fifordaddr[2] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "led2buf FX2FD\[7\] gclk 10.108 ns register " "Info: tsu for register \"led2buf\" (data pin = \"FX2FD\[7\]\", clock pin = \"gclk\") is 10.108 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.033 ns + Longest pin register " "Info: + Longest pin to register delay is 13.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FX2FD\[7\] 1 PIN PIN_233 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_233; Fanout = 1; PIN Node = 'FX2FD\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { FX2FD[7] } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns FX2FD\[7\]~8 2 COMB IOC_X6_Y21_N1 3 " "Info: 2: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = IOC_X6_Y21_N1; Fanout = 3; COMB Node = 'FX2FD\[7\]~8'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.475 ns" { FX2FD[7] FX2FD[7]~8 } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.843 ns) + CELL(0.292 ns) 9.610 ns process0~193 3 COMB LC_X19_Y18_N6 1 " "Info: 3: + IC(7.843 ns) + CELL(0.292 ns) = 9.610 ns; Loc. = LC_X19_Y18_N6; Fanout = 1; COMB Node = 'process0~193'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "8.135 ns" { FX2FD[7]~8 process0~193 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.590 ns) 10.635 ns process0~195 4 COMB LC_X19_Y18_N2 1 " "Info: 4: + IC(0.435 ns) + CELL(0.590 ns) = 10.635 ns; Loc. = LC_X19_Y18_N2; Fanout = 1; COMB Node = 'process0~195'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.025 ns" { process0~193 process0~195 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.536 ns) + CELL(0.114 ns) 12.285 ns process0~0 5 COMB LC_X21_Y16_N3 1 " "Info: 5: + IC(1.536 ns) + CELL(0.114 ns) = 12.285 ns; Loc. = LC_X21_Y16_N3; Fanout = 1; COMB Node = 'process0~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.650 ns" { process0~195 process0~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.309 ns) 13.033 ns led2buf 6 REG LC_X21_Y16_N5 2 " "Info: 6: + IC(0.439 ns) + CELL(0.309 ns) = 13.033 ns; Loc. = LC_X21_Y16_N5; Fanout = 2; REG Node = 'led2buf'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "0.748 ns" { process0~0 led2buf } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.780 ns ( 21.33 % ) " "Info: Total cell delay = 2.780 ns ( 21.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.253 ns ( 78.67 % ) " "Info: Total interconnect delay = 10.253 ns ( 78.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "13.033 ns" { FX2FD[7] FX2FD[7]~8 process0~193 process0~195 process0~0 led2buf } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.033 ns" { FX2FD[7] FX2FD[7]~8 process0~193 process0~195 process0~0 led2buf } { 0.000ns 0.000ns 7.843ns 0.435ns 1.536ns 0.439ns } { 0.000ns 1.475ns 0.292ns 0.590ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 97 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gclk destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"gclk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns gclk 1 CLK PIN_28 184 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 184; CLK Node = 'gclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { gclk } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns led2buf 2 REG LC_X21_Y16_N5 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X21_Y16_N5; Fanout = 2; REG Node = 'led2buf'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "1.493 ns" { gclk led2buf } "NODE_NAME" } "" } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.962 ns" { gclk led2buf } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { gclk gclk~out0 led2buf } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "13.033 ns" { FX2FD[7] FX2FD[7]~8 process0~193 process0~195 process0~0 led2buf } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.033 ns" { FX2FD[7] FX2FD[7]~8 process0~193 process0~195 process0~0 led2buf } { 0.000ns 0.000ns 7.843ns 0.435ns 1.536ns 0.439ns } { 0.000ns 1.475ns 0.292ns 0.590ns 0.114ns 0.309ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "2.962 ns" { gclk led2buf } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { gclk gclk~out0 led2buf } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}