📄 usb_fpga.map.qmsg
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{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMFD\[4\] USB_FPGA.vhd(38) " "Warning (10034): Output port \"SRAMFD\[4\]\" at USB_FPGA.vhd(38) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMFD\[3\] USB_FPGA.vhd(38) " "Warning (10034): Output port \"SRAMFD\[3\]\" at USB_FPGA.vhd(38) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMFD\[2\] USB_FPGA.vhd(38) " "Warning (10034): Output port \"SRAMFD\[2\]\" at USB_FPGA.vhd(38) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMFD\[1\] USB_FPGA.vhd(38) " "Warning (10034): Output port \"SRAMFD\[1\]\" at USB_FPGA.vhd(38) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMFD\[0\] USB_FPGA.vhd(38) " "Warning (10034): Output port \"SRAMFD\[0\]\" at USB_FPGA.vhd(38) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMWE USB_FPGA.vhd(40) " "Warning (10034): Output port \"SRAMWE\" at USB_FPGA.vhd(40) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 40 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMCE USB_FPGA.vhd(41) " "Warning (10034): Output port \"SRAMCE\" at USB_FPGA.vhd(41) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 41 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMOE USB_FPGA.vhd(42) " "Warning (10034): Output port \"SRAMOE\" at USB_FPGA.vhd(42) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 42 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMUB USB_FPGA.vhd(43) " "Warning (10034): Output port \"SRAMUB\" at USB_FPGA.vhd(43) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 43 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "SRAMLB USB_FPGA.vhd(44) " "Warning (10034): Output port \"SRAMLB\" at USB_FPGA.vhd(44) has no driver" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 44 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~21 process1~0 " "Info: Duplicate register \"process1~21\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~19 process1~0 " "Info: Duplicate register \"process1~19\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~17 process1~0 " "Info: Duplicate register \"process1~17\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~15 process1~0 " "Info: Duplicate register \"process1~15\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~13 process1~0 " "Info: Duplicate register \"process1~13\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~11 process1~0 " "Info: Duplicate register \"process1~11\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~9 process1~0 " "Info: Duplicate register \"process1~9\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~7 process1~0 " "Info: Duplicate register \"process1~7\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~5 process1~0 " "Info: Duplicate register \"process1~5\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~3 process1~0 " "Info: Duplicate register \"process1~3\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~1 process1~0 " "Info: Duplicate register \"process1~1\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~23 process1~0 " "Info: Duplicate register \"process1~23\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~25 process1~0 " "Info: Duplicate register \"process1~25\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~29 process1~0 " "Info: Duplicate register \"process1~29\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "process1~27 process1~0 " "Info: Duplicate register \"process1~27\" merged to single register \"process1~0\"" { } { } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} } { } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "fifomemory~1 " "Warning: Created node \"fifomemory~1\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." { } { { "USB_FPGA.vhd" "fifomemory~1" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 62 -1 0 } } } 0 0 "Created node \"%1!s!\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "fifomemory~1 1024 16 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=1024, WIDTH_A=16) from the following design logic: \"fifomemory~1\"" { } { { "USB_FPGA.vhd" "fifomemory~1" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 62 -1 0 } } } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0} } { } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" { } { { "altsyncram.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lk81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lk81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lk81 " "Info: Found entity 1: altsyncram_lk81" { } { { "db/altsyncram_lk81.tdf" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/altsyncram_lk81.tdf" 36 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "RDY2 GND " "Warning: Pin \"RDY2\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 33 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RDY3 GND " "Warning: Pin \"RDY3\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 34 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RDY4 GND " "Warning: Pin \"RDY4\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 35 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RDY5 GND " "Warning: Pin \"RDY5\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 36 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[0\] GND " "Warning: Pin \"SRAMFD\[0\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[1\] GND " "Warning: Pin \"SRAMFD\[1\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[2\] GND " "Warning: Pin \"SRAMFD\[2\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[3\] GND " "Warning: Pin \"SRAMFD\[3\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[4\] GND " "Warning: Pin \"SRAMFD\[4\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[5\] GND " "Warning: Pin \"SRAMFD\[5\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[6\] GND " "Warning: Pin \"SRAMFD\[6\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[7\] GND " "Warning: Pin \"SRAMFD\[7\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[8\] GND " "Warning: Pin \"SRAMFD\[8\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[9\] GND " "Warning: Pin \"SRAMFD\[9\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[10\] GND " "Warning: Pin \"SRAMFD\[10\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[11\] GND " "Warning: Pin \"SRAMFD\[11\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[12\] GND " "Warning: Pin \"SRAMFD\[12\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[13\] GND " "Warning: Pin \"SRAMFD\[13\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[14\] GND " "Warning: Pin \"SRAMFD\[14\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMFD\[15\] GND " "Warning: Pin \"SRAMFD\[15\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[9\] GND " "Warning: Pin \"SRAMADR\[9\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[10\] GND " "Warning: Pin \"SRAMADR\[10\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[11\] GND " "Warning: Pin \"SRAMADR\[11\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[12\] GND " "Warning: Pin \"SRAMADR\[12\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[13\] GND " "Warning: Pin \"SRAMADR\[13\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[14\] GND " "Warning: Pin \"SRAMADR\[14\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[15\] GND " "Warning: Pin \"SRAMADR\[15\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[16\] GND " "Warning: Pin \"SRAMADR\[16\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMADR\[17\] GND " "Warning: Pin \"SRAMADR\[17\]\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMWE GND " "Warning: Pin \"SRAMWE\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 40 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMCE GND " "Warning: Pin \"SRAMCE\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 41 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMOE GND " "Warning: Pin \"SRAMOE\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 42 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMUB GND " "Warning: Pin \"SRAMUB\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 43 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SRAMLB GND " "Warning: Pin \"SRAMLB\" stuck at GND" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 44 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 97 -1 0 } } { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 121 -1 0 } } } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "5 " "Warning: Design contains 5 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CTL3 " "Warning: No output dependent on input pin \"CTL3\"" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 27 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CTL4 " "Warning: No output dependent on input pin \"CTL4\"" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 28 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CTL5 " "Warning: No output dependent on input pin \"CTL5\"" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 29 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "KEY2 " "Warning: No output dependent on input pin \"KEY2\"" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 52 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "KEY4 " "Warning: No output dependent on input pin \"KEY4\"" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 54 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "246 " "Info: Implemented 246 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "21 " "Info: Implemented 21 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "49 " "Info: Implemented 49 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "144 " "Info: Implemented 144 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" { } { } 0 0 "Implemented %1!d! RAM segments" 0 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 67 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 67 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 30 20:34:36 2007 " "Info: Processing ended: Tue Oct 30 20:34:36 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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