usb_fpga.map.eqn

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

--C1_q_b[10] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[10]_PORT_A_data_in = A1L176;
C1_q_b[10]_PORT_A_data_in_reg = DFFE(C1_q_b[10]_PORT_A_data_in, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[10]_PORT_A_address_reg = DFFE(C1_q_b[10]_PORT_A_address, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[10]_PORT_B_address_reg = DFFE(C1_q_b[10]_PORT_B_address, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_PORT_A_write_enable = VCC;
C1_q_b[10]_PORT_A_write_enable_reg = DFFE(C1_q_b[10]_PORT_A_write_enable, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_read_enable = VCC;
C1_q_b[10]_PORT_B_read_enable_reg = DFFE(C1_q_b[10]_PORT_B_read_enable, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_clock_0 = gclk;
C1_q_b[10]_clock_1 = gclk;
C1_q_b[10]_clock_enable_0 = A1L98;
C1_q_b[10]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[10]_PORT_B_data_out = MEMORY(C1_q_b[10]_PORT_A_data_in_reg, , C1_q_b[10]_PORT_A_address_reg, C1_q_b[10]_PORT_B_address_reg, C1_q_b[10]_PORT_A_write_enable_reg, C1_q_b[10]_PORT_B_read_enable_reg, , , C1_q_b[10]_clock_0, C1_q_b[10]_clock_1, C1_q_b[10]_clock_enable_0, C1_q_b[10]_clock_enable_1, , );
C1_q_b[10] = C1_q_b[10]_PORT_B_data_out[0];


--A1L92Q is fifomemory~24
--operation mode is normal

A1L92Q_lut_out = A1L176;
A1L92Q = DFFEAS(A1L92Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[11] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[11]_PORT_A_data_in = A1L179;
C1_q_b[11]_PORT_A_data_in_reg = DFFE(C1_q_b[11]_PORT_A_data_in, C1_q_b[11]_clock_0, , , C1_q_b[11]_clock_enable_0);
C1_q_b[11]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[11]_PORT_A_address_reg = DFFE(C1_q_b[11]_PORT_A_address, C1_q_b[11]_clock_0, , , C1_q_b[11]_clock_enable_0);
C1_q_b[11]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[11]_PORT_B_address_reg = DFFE(C1_q_b[11]_PORT_B_address, C1_q_b[11]_clock_1, , , C1_q_b[11]_clock_enable_1);
C1_q_b[11]_PORT_A_write_enable = VCC;
C1_q_b[11]_PORT_A_write_enable_reg = DFFE(C1_q_b[11]_PORT_A_write_enable, C1_q_b[11]_clock_0, , , C1_q_b[11]_clock_enable_0);
C1_q_b[11]_PORT_B_read_enable = VCC;
C1_q_b[11]_PORT_B_read_enable_reg = DFFE(C1_q_b[11]_PORT_B_read_enable, C1_q_b[11]_clock_1, , , C1_q_b[11]_clock_enable_1);
C1_q_b[11]_clock_0 = gclk;
C1_q_b[11]_clock_1 = gclk;
C1_q_b[11]_clock_enable_0 = A1L98;
C1_q_b[11]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[11]_PORT_B_data_out = MEMORY(C1_q_b[11]_PORT_A_data_in_reg, , C1_q_b[11]_PORT_A_address_reg, C1_q_b[11]_PORT_B_address_reg, C1_q_b[11]_PORT_A_write_enable_reg, C1_q_b[11]_PORT_B_read_enable_reg, , , C1_q_b[11]_clock_0, C1_q_b[11]_clock_1, C1_q_b[11]_clock_enable_0, C1_q_b[11]_clock_enable_1, , );
C1_q_b[11] = C1_q_b[11]_PORT_B_data_out[0];


--A1L93Q is fifomemory~26
--operation mode is normal

A1L93Q_lut_out = A1L179;
A1L93Q = DFFEAS(A1L93Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[12] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[12]_PORT_A_data_in = A1L182;
C1_q_b[12]_PORT_A_data_in_reg = DFFE(C1_q_b[12]_PORT_A_data_in, C1_q_b[12]_clock_0, , , C1_q_b[12]_clock_enable_0);
C1_q_b[12]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[12]_PORT_A_address_reg = DFFE(C1_q_b[12]_PORT_A_address, C1_q_b[12]_clock_0, , , C1_q_b[12]_clock_enable_0);
C1_q_b[12]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[12]_PORT_B_address_reg = DFFE(C1_q_b[12]_PORT_B_address, C1_q_b[12]_clock_1, , , C1_q_b[12]_clock_enable_1);
C1_q_b[12]_PORT_A_write_enable = VCC;
C1_q_b[12]_PORT_A_write_enable_reg = DFFE(C1_q_b[12]_PORT_A_write_enable, C1_q_b[12]_clock_0, , , C1_q_b[12]_clock_enable_0);
C1_q_b[12]_PORT_B_read_enable = VCC;
C1_q_b[12]_PORT_B_read_enable_reg = DFFE(C1_q_b[12]_PORT_B_read_enable, C1_q_b[12]_clock_1, , , C1_q_b[12]_clock_enable_1);
C1_q_b[12]_clock_0 = gclk;
C1_q_b[12]_clock_1 = gclk;
C1_q_b[12]_clock_enable_0 = A1L98;
C1_q_b[12]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[12]_PORT_B_data_out = MEMORY(C1_q_b[12]_PORT_A_data_in_reg, , C1_q_b[12]_PORT_A_address_reg, C1_q_b[12]_PORT_B_address_reg, C1_q_b[12]_PORT_A_write_enable_reg, C1_q_b[12]_PORT_B_read_enable_reg, , , C1_q_b[12]_clock_0, C1_q_b[12]_clock_1, C1_q_b[12]_clock_enable_0, C1_q_b[12]_clock_enable_1, , );
C1_q_b[12] = C1_q_b[12]_PORT_B_data_out[0];


--A1L94Q is fifomemory~28
--operation mode is normal

A1L94Q_lut_out = A1L182;
A1L94Q = DFFEAS(A1L94Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[13] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[13]_PORT_A_data_in = A1L185;
C1_q_b[13]_PORT_A_data_in_reg = DFFE(C1_q_b[13]_PORT_A_data_in, C1_q_b[13]_clock_0, , , C1_q_b[13]_clock_enable_0);
C1_q_b[13]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[13]_PORT_A_address_reg = DFFE(C1_q_b[13]_PORT_A_address, C1_q_b[13]_clock_0, , , C1_q_b[13]_clock_enable_0);
C1_q_b[13]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[13]_PORT_B_address_reg = DFFE(C1_q_b[13]_PORT_B_address, C1_q_b[13]_clock_1, , , C1_q_b[13]_clock_enable_1);
C1_q_b[13]_PORT_A_write_enable = VCC;
C1_q_b[13]_PORT_A_write_enable_reg = DFFE(C1_q_b[13]_PORT_A_write_enable, C1_q_b[13]_clock_0, , , C1_q_b[13]_clock_enable_0);
C1_q_b[13]_PORT_B_read_enable = VCC;
C1_q_b[13]_PORT_B_read_enable_reg = DFFE(C1_q_b[13]_PORT_B_read_enable, C1_q_b[13]_clock_1, , , C1_q_b[13]_clock_enable_1);
C1_q_b[13]_clock_0 = gclk;
C1_q_b[13]_clock_1 = gclk;
C1_q_b[13]_clock_enable_0 = A1L98;
C1_q_b[13]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[13]_PORT_B_data_out = MEMORY(C1_q_b[13]_PORT_A_data_in_reg, , C1_q_b[13]_PORT_A_address_reg, C1_q_b[13]_PORT_B_address_reg, C1_q_b[13]_PORT_A_write_enable_reg, C1_q_b[13]_PORT_B_read_enable_reg, , , C1_q_b[13]_clock_0, C1_q_b[13]_clock_1, C1_q_b[13]_clock_enable_0, C1_q_b[13]_clock_enable_1, , );
C1_q_b[13] = C1_q_b[13]_PORT_B_data_out[0];


--A1L95Q is fifomemory~30
--operation mode is normal

A1L95Q_lut_out = A1L185;
A1L95Q = DFFEAS(A1L95Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[14] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[14]_PORT_A_data_in = A1L188;
C1_q_b[14]_PORT_A_data_in_reg = DFFE(C1_q_b[14]_PORT_A_data_in, C1_q_b[14]_clock_0, , , C1_q_b[14]_clock_enable_0);
C1_q_b[14]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[14]_PORT_A_address_reg = DFFE(C1_q_b[14]_PORT_A_address, C1_q_b[14]_clock_0, , , C1_q_b[14]_clock_enable_0);
C1_q_b[14]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[14]_PORT_B_address_reg = DFFE(C1_q_b[14]_PORT_B_address, C1_q_b[14]_clock_1, , , C1_q_b[14]_clock_enable_1);
C1_q_b[14]_PORT_A_write_enable = VCC;
C1_q_b[14]_PORT_A_write_enable_reg = DFFE(C1_q_b[14]_PORT_A_write_enable, C1_q_b[14]_clock_0, , , C1_q_b[14]_clock_enable_0);
C1_q_b[14]_PORT_B_read_enable = VCC;
C1_q_b[14]_PORT_B_read_enable_reg = DFFE(C1_q_b[14]_PORT_B_read_enable, C1_q_b[14]_clock_1, , , C1_q_b[14]_clock_enable_1);
C1_q_b[14]_clock_0 = gclk;
C1_q_b[14]_clock_1 = gclk;
C1_q_b[14]_clock_enable_0 = A1L98;
C1_q_b[14]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[14]_PORT_B_data_out = MEMORY(C1_q_b[14]_PORT_A_data_in_reg, , C1_q_b[14]_PORT_A_address_reg, C1_q_b[14]_PORT_B_address_reg, C1_q_b[14]_PORT_A_write_enable_reg, C1_q_b[14]_PORT_B_read_enable_reg, , , C1_q_b[14]_clock_0, C1_q_b[14]_clock_1, C1_q_b[14]_clock_enable_0, C1_q_b[14]_clock_enable_1, , );
C1_q_b[14] = C1_q_b[14]_PORT_B_data_out[0];


--A1L96Q is fifomemory~32
--operation mode is normal

A1L96Q_lut_out = A1L188;
A1L96Q = DFFEAS(A1L96Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[15] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[15]_PORT_A_data_in = A1L191;
C1_q_b[15]_PORT_A_data_in_reg = DFFE(C1_q_b[15]_PORT_A_data_in, C1_q_b[15]_clock_0, , , C1_q_b[15]_clock_enable_0);
C1_q_b[15]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[15]_PORT_A_address_reg = DFFE(C1_q_b[15]_PORT_A_address, C1_q_b[15]_clock_0, , , C1_q_b[15]_clock_enable_0);
C1_q_b[15]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[15]_PORT_B_address_reg = DFFE(C1_q_b[15]_PORT_B_address, C1_q_b[15]_clock_1, , , C1_q_b[15]_clock_enable_1);
C1_q_b[15]_PORT_A_write_enable = VCC;
C1_q_b[15]_PORT_A_write_enable_reg = DFFE(C1_q_b[15]_PORT_A_write_enable, C1_q_b[15]_clock_0, , , C1_q_b[15]_clock_enable_0);
C1_q_b[15]_PORT_B_read_enable = VCC;
C1_q_b[15]_PORT_B_read_enable_reg = DFFE(C1_q_b[15]_PORT_B_read_enable, C1_q_b[15]_clock_1, , , C1_q_b[15]_clock_enable_1);
C1_q_b[15]_clock_0 = gclk;
C1_q_b[15]_clock_1 = gclk;
C1_q_b[15]_clock_enable_0 = A1L98;
C1_q_b[15]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[15]_PORT_B_data_out = MEMORY(C1_q_b[15]_PORT_A_data_in_reg, , C1_q_b[15]_PORT_A_address_reg, C1_q_b[15]_PORT_B_address_reg, C1_q_b[15]_PORT_A_write_enable_reg, C1_q_b[15]_PORT_B_read_enable_reg, , , C1_q_b[15]_clock_0, C1_q_b[15]_clock_1, C1_q_b[15]_clock_enable_0, C1_q_b[15]_clock_enable_1, , );
C1_q_b[15] = C1_q_b[15]_PORT_B_data_out[0];


--A1L97Q is fifomemory~34
--operation mode is normal

A1L97Q_lut_out = A1L191;
A1L97Q = DFFEAS(A1L97Q_lut_out, gclk, VCC, , A1L102, , , , );


--A1L215 is LessThan~435
--operation mode is arithmetic

A1L215 = CARRY(fifordaddr[4] & fifowraddr[4] & !A1L217 # !fifordaddr[4] & (fifowraddr[4] # !A1L217));


--A1L98 is fifomemory~309
--operation mode is normal

A1L98 = !CTL0_FLAGA & (RESETFPGA);


--A1L99 is fifomemory~310
--operation mode is normal

A1L99 = !fifowraddr[7] & !fifowraddr[9];


--A1L100 is fifomemory~311
--operation mode is normal

A1L100 = !fifowraddr[0] & !fifowraddr[1] & !fifowraddr[3] & !fifowraddr[5];


--A1L101 is fifomemory~312
--operation mode is normal

A1L101 = !fifowraddr[6] & !fifowraddr[2] & !fifowraddr[4] & !fifowraddr[8];


--A1L102 is fifomemory~313
--operation mode is normal

A1L102 = A1L99 & A1L100 & A1L101 & A1L98;


--A1L217 is LessThan~440
--operation mode is arithmetic

A1L217 = CARRY(fifordaddr[3] & (!A1L219 # !fifowraddr[3]) # !fifordaddr[3] & !fifowraddr[3] & !A1L219);


--A1L219 is LessThan~445
--operation mode is arithmetic

A1L219 = CARRY(fifordaddr[2] & fifowraddr[2] & !A1L221 # !fifordaddr[2] & (fifowraddr[2] # !A1L221));


--A1L221 is LessThan~450
--operation mode is arithmetic

A1L221 = CARRY(fifordaddr[1] & (!A1L223 # !fifowraddr[1]) # !fifordaddr[1] & !fifowraddr[1] & !A1L223);


--A1L223 is LessThan~455
--operation mode is arithmetic

A1L223 = CARRY(!fifordaddr[0] & fifowraddr[0]);


--CTL3 is CTL3
--operation mode is input

CTL3 = INPUT();


--CTL4 is CTL4
--operation mode is input

CTL4 = INPUT();


--CTL5 is CTL5
--operation mode is input

CTL5 = INPUT();


--KEY2 is KEY2
--operation mode is input

KEY2 = INPUT();


--KEY4 is KEY4
--operation mode is input

KEY4 = INPUT();


--RESETFPGA is RESETFPGA
--operation mode is input

RESETFPGA = INPUT();


--FX2ADR[0] is FX2ADR[0]
--operation mode is input

FX2ADR[0] = INPUT();


--FX2ADR[1] is FX2ADR[1]
--operation mode is input

FX2ADR[1] = INPUT();


--FX2ADR[2] is FX2ADR[2]
--operation mode is input

FX2ADR[2] = INPUT();


--FX2ADR[3] is FX2ADR[3]
--operation mode is input

FX2ADR[3] = INPUT();


--FX2ADR[4] is FX2ADR[4]
--operation mode is input

FX2ADR[4] = INPUT();


--FX2ADR[5] is FX2ADR[5]
--operation mode is input

FX2ADR[5] = INPUT();


--FX2ADR[6] is FX2ADR[6]
--operation mode is input

FX2ADR[6] = INPUT();


--FX2ADR[7] is FX2ADR[7]
--operation mode is input

FX2ADR[7] = INPUT();


--FX2ADR[8] is FX2ADR[8]
--operation mode is input

FX2ADR[8] = INPUT();


--KEY1 is KEY1
--operation mode is input

KEY1 = INPUT();


--KEY3 is KEY3
--operation mode is input

KEY3 = INPUT();


--gclk is gclk
--operation mode is input

gclk = INPUT();


--CTL0_FLAGA is CTL0_FLAGA
--operation mode is input

CTL0_FLAGA = INPUT();


--CTL1_FLAGB is CTL1_FLAGB
--operation mode is input

CTL1_FLAGB = INPUT();


--CTL2_FLAGC is CTL2_FLAGC
--operation mode is input

CTL2_FLAGC = INPUT();


--RDY0_SLRD is RDY0_SLRD
--operation mode is output

RDY0_SLRD = OUTPUT(A1L75);


--RDY1_SLWR is RDY1_SLWR
--operation mode is output

RDY1_SLWR = OUTPUT(A1L80);


--RDY2 is RDY2
--operation mode is output

RDY2 = OUTPUT(GND);


--RDY3 is RDY3
--operation mode is output

RDY3 = OUTPUT(GND);


--RDY4 is RDY4
--operation mode is output

RDY4 = OUTPUT(GND);


--RDY5 is RDY5
--operation mode is output

RDY5 = OUTPUT(GND);


--SRAMFD[0] is SRAMFD[0]
--operation mode is output

SRAMFD[0] = OUTPUT(GND);


--SRAMFD[1] is SRAMFD[1]
--operation mode is output

SRAMFD[1] = OUTPUT(GND);