usb_fpga.map.eqn

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

--operation mode is normal

data2usb[2]_lut_out = A1L81Q & C1_q_b[2] # !A1L81Q & (A1L84Q);
data2usb[2] = DFFEAS(data2usb[2]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[3] is data2usb[3]
--operation mode is normal

data2usb[3]_lut_out = A1L81Q & C1_q_b[3] # !A1L81Q & (A1L85Q);
data2usb[3] = DFFEAS(data2usb[3]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[4] is data2usb[4]
--operation mode is normal

data2usb[4]_lut_out = A1L81Q & C1_q_b[4] # !A1L81Q & (A1L86Q);
data2usb[4] = DFFEAS(data2usb[4]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[5] is data2usb[5]
--operation mode is normal

data2usb[5]_lut_out = A1L81Q & C1_q_b[5] # !A1L81Q & (A1L87Q);
data2usb[5] = DFFEAS(data2usb[5]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[6] is data2usb[6]
--operation mode is normal

data2usb[6]_lut_out = A1L81Q & C1_q_b[6] # !A1L81Q & (A1L88Q);
data2usb[6] = DFFEAS(data2usb[6]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[7] is data2usb[7]
--operation mode is normal

data2usb[7]_lut_out = A1L81Q & C1_q_b[7] # !A1L81Q & (A1L89Q);
data2usb[7] = DFFEAS(data2usb[7]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[8] is data2usb[8]
--operation mode is normal

data2usb[8]_lut_out = A1L81Q & C1_q_b[8] # !A1L81Q & (A1L90Q);
data2usb[8] = DFFEAS(data2usb[8]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[9] is data2usb[9]
--operation mode is normal

data2usb[9]_lut_out = A1L81Q & C1_q_b[9] # !A1L81Q & (A1L91Q);
data2usb[9] = DFFEAS(data2usb[9]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[10] is data2usb[10]
--operation mode is normal

data2usb[10]_lut_out = A1L81Q & C1_q_b[10] # !A1L81Q & (A1L92Q);
data2usb[10] = DFFEAS(data2usb[10]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[11] is data2usb[11]
--operation mode is normal

data2usb[11]_lut_out = A1L81Q & C1_q_b[11] # !A1L81Q & (A1L93Q);
data2usb[11] = DFFEAS(data2usb[11]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[12] is data2usb[12]
--operation mode is normal

data2usb[12]_lut_out = A1L81Q & C1_q_b[12] # !A1L81Q & (A1L94Q);
data2usb[12] = DFFEAS(data2usb[12]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[13] is data2usb[13]
--operation mode is normal

data2usb[13]_lut_out = A1L81Q & C1_q_b[13] # !A1L81Q & (A1L95Q);
data2usb[13] = DFFEAS(data2usb[13]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[14] is data2usb[14]
--operation mode is normal

data2usb[14]_lut_out = A1L81Q & C1_q_b[14] # !A1L81Q & (A1L96Q);
data2usb[14] = DFFEAS(data2usb[14]_lut_out, gclk, VCC, , A1L59, , , , );


--data2usb[15] is data2usb[15]
--operation mode is normal

data2usb[15]_lut_out = A1L81Q & C1_q_b[15] # !A1L81Q & (A1L97Q);
data2usb[15] = DFFEAS(data2usb[15]_lut_out, gclk, VCC, , A1L59, , , , );


--A1L213 is LessThan~430
--operation mode is arithmetic

A1L213 = CARRY(fifordaddr[5] & (!A1L215 # !fifowraddr[5]) # !fifordaddr[5] & !fifowraddr[5] & !A1L215);


--C1_q_b[0] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[0]_PORT_A_data_in = A1L146;
C1_q_b[0]_PORT_A_data_in_reg = DFFE(C1_q_b[0]_PORT_A_data_in, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[0]_PORT_A_address_reg = DFFE(C1_q_b[0]_PORT_A_address, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[0]_PORT_B_address_reg = DFFE(C1_q_b[0]_PORT_B_address, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_PORT_A_write_enable = VCC;
C1_q_b[0]_PORT_A_write_enable_reg = DFFE(C1_q_b[0]_PORT_A_write_enable, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_read_enable = VCC;
C1_q_b[0]_PORT_B_read_enable_reg = DFFE(C1_q_b[0]_PORT_B_read_enable, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_clock_0 = gclk;
C1_q_b[0]_clock_1 = gclk;
C1_q_b[0]_clock_enable_0 = A1L98;
C1_q_b[0]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[0]_PORT_B_data_out = MEMORY(C1_q_b[0]_PORT_A_data_in_reg, , C1_q_b[0]_PORT_A_address_reg, C1_q_b[0]_PORT_B_address_reg, C1_q_b[0]_PORT_A_write_enable_reg, C1_q_b[0]_PORT_B_read_enable_reg, , , C1_q_b[0]_clock_0, C1_q_b[0]_clock_1, C1_q_b[0]_clock_enable_0, C1_q_b[0]_clock_enable_1, , );
C1_q_b[0] = C1_q_b[0]_PORT_B_data_out[0];


--A1L82Q is fifomemory~4
--operation mode is normal

A1L82Q_lut_out = A1L146;
A1L82Q = DFFEAS(A1L82Q_lut_out, gclk, VCC, , A1L102, , , , );


--A1L81Q is fifomemory~3
--operation mode is normal

A1L81Q_lut_out = VCC;
A1L81Q = DFFEAS(A1L81Q_lut_out, gclk, RESETFPGA, , !CTL1_FLAGB, , , , );


--A1L59 is data2usb[0]~15
--operation mode is normal

A1L59 = RESETFPGA & (!CTL1_FLAGB);


--C1_q_b[1] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[1]_PORT_A_data_in = A1L149;
C1_q_b[1]_PORT_A_data_in_reg = DFFE(C1_q_b[1]_PORT_A_data_in, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[1]_PORT_A_address_reg = DFFE(C1_q_b[1]_PORT_A_address, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[1]_PORT_B_address_reg = DFFE(C1_q_b[1]_PORT_B_address, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_PORT_A_write_enable = VCC;
C1_q_b[1]_PORT_A_write_enable_reg = DFFE(C1_q_b[1]_PORT_A_write_enable, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_read_enable = VCC;
C1_q_b[1]_PORT_B_read_enable_reg = DFFE(C1_q_b[1]_PORT_B_read_enable, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_clock_0 = gclk;
C1_q_b[1]_clock_1 = gclk;
C1_q_b[1]_clock_enable_0 = A1L98;
C1_q_b[1]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[1]_PORT_B_data_out = MEMORY(C1_q_b[1]_PORT_A_data_in_reg, , C1_q_b[1]_PORT_A_address_reg, C1_q_b[1]_PORT_B_address_reg, C1_q_b[1]_PORT_A_write_enable_reg, C1_q_b[1]_PORT_B_read_enable_reg, , , C1_q_b[1]_clock_0, C1_q_b[1]_clock_1, C1_q_b[1]_clock_enable_0, C1_q_b[1]_clock_enable_1, , );
C1_q_b[1] = C1_q_b[1]_PORT_B_data_out[0];


--A1L83Q is fifomemory~6
--operation mode is normal

A1L83Q_lut_out = A1L149;
A1L83Q = DFFEAS(A1L83Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[2] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[2]_PORT_A_data_in = A1L152;
C1_q_b[2]_PORT_A_data_in_reg = DFFE(C1_q_b[2]_PORT_A_data_in, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[2]_PORT_A_address_reg = DFFE(C1_q_b[2]_PORT_A_address, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[2]_PORT_B_address_reg = DFFE(C1_q_b[2]_PORT_B_address, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_PORT_A_write_enable = VCC;
C1_q_b[2]_PORT_A_write_enable_reg = DFFE(C1_q_b[2]_PORT_A_write_enable, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_read_enable = VCC;
C1_q_b[2]_PORT_B_read_enable_reg = DFFE(C1_q_b[2]_PORT_B_read_enable, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_clock_0 = gclk;
C1_q_b[2]_clock_1 = gclk;
C1_q_b[2]_clock_enable_0 = A1L98;
C1_q_b[2]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[2]_PORT_B_data_out = MEMORY(C1_q_b[2]_PORT_A_data_in_reg, , C1_q_b[2]_PORT_A_address_reg, C1_q_b[2]_PORT_B_address_reg, C1_q_b[2]_PORT_A_write_enable_reg, C1_q_b[2]_PORT_B_read_enable_reg, , , C1_q_b[2]_clock_0, C1_q_b[2]_clock_1, C1_q_b[2]_clock_enable_0, C1_q_b[2]_clock_enable_1, , );
C1_q_b[2] = C1_q_b[2]_PORT_B_data_out[0];


--A1L84Q is fifomemory~8
--operation mode is normal

A1L84Q_lut_out = A1L152;
A1L84Q = DFFEAS(A1L84Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[3] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[3]_PORT_A_data_in = A1L155;
C1_q_b[3]_PORT_A_data_in_reg = DFFE(C1_q_b[3]_PORT_A_data_in, C1_q_b[3]_clock_0, , , C1_q_b[3]_clock_enable_0);
C1_q_b[3]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[3]_PORT_A_address_reg = DFFE(C1_q_b[3]_PORT_A_address, C1_q_b[3]_clock_0, , , C1_q_b[3]_clock_enable_0);
C1_q_b[3]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[3]_PORT_B_address_reg = DFFE(C1_q_b[3]_PORT_B_address, C1_q_b[3]_clock_1, , , C1_q_b[3]_clock_enable_1);
C1_q_b[3]_PORT_A_write_enable = VCC;
C1_q_b[3]_PORT_A_write_enable_reg = DFFE(C1_q_b[3]_PORT_A_write_enable, C1_q_b[3]_clock_0, , , C1_q_b[3]_clock_enable_0);
C1_q_b[3]_PORT_B_read_enable = VCC;
C1_q_b[3]_PORT_B_read_enable_reg = DFFE(C1_q_b[3]_PORT_B_read_enable, C1_q_b[3]_clock_1, , , C1_q_b[3]_clock_enable_1);
C1_q_b[3]_clock_0 = gclk;
C1_q_b[3]_clock_1 = gclk;
C1_q_b[3]_clock_enable_0 = A1L98;
C1_q_b[3]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[3]_PORT_B_data_out = MEMORY(C1_q_b[3]_PORT_A_data_in_reg, , C1_q_b[3]_PORT_A_address_reg, C1_q_b[3]_PORT_B_address_reg, C1_q_b[3]_PORT_A_write_enable_reg, C1_q_b[3]_PORT_B_read_enable_reg, , , C1_q_b[3]_clock_0, C1_q_b[3]_clock_1, C1_q_b[3]_clock_enable_0, C1_q_b[3]_clock_enable_1, , );
C1_q_b[3] = C1_q_b[3]_PORT_B_data_out[0];


--A1L85Q is fifomemory~10
--operation mode is normal

A1L85Q_lut_out = A1L155;
A1L85Q = DFFEAS(A1L85Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[4] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[4]_PORT_A_data_in = A1L158;
C1_q_b[4]_PORT_A_data_in_reg = DFFE(C1_q_b[4]_PORT_A_data_in, C1_q_b[4]_clock_0, , , C1_q_b[4]_clock_enable_0);
C1_q_b[4]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[4]_PORT_A_address_reg = DFFE(C1_q_b[4]_PORT_A_address, C1_q_b[4]_clock_0, , , C1_q_b[4]_clock_enable_0);
C1_q_b[4]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[4]_PORT_B_address_reg = DFFE(C1_q_b[4]_PORT_B_address, C1_q_b[4]_clock_1, , , C1_q_b[4]_clock_enable_1);
C1_q_b[4]_PORT_A_write_enable = VCC;
C1_q_b[4]_PORT_A_write_enable_reg = DFFE(C1_q_b[4]_PORT_A_write_enable, C1_q_b[4]_clock_0, , , C1_q_b[4]_clock_enable_0);
C1_q_b[4]_PORT_B_read_enable = VCC;
C1_q_b[4]_PORT_B_read_enable_reg = DFFE(C1_q_b[4]_PORT_B_read_enable, C1_q_b[4]_clock_1, , , C1_q_b[4]_clock_enable_1);
C1_q_b[4]_clock_0 = gclk;
C1_q_b[4]_clock_1 = gclk;
C1_q_b[4]_clock_enable_0 = A1L98;
C1_q_b[4]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[4]_PORT_B_data_out = MEMORY(C1_q_b[4]_PORT_A_data_in_reg, , C1_q_b[4]_PORT_A_address_reg, C1_q_b[4]_PORT_B_address_reg, C1_q_b[4]_PORT_A_write_enable_reg, C1_q_b[4]_PORT_B_read_enable_reg, , , C1_q_b[4]_clock_0, C1_q_b[4]_clock_1, C1_q_b[4]_clock_enable_0, C1_q_b[4]_clock_enable_1, , );
C1_q_b[4] = C1_q_b[4]_PORT_B_data_out[0];


--A1L86Q is fifomemory~12
--operation mode is normal

A1L86Q_lut_out = A1L158;
A1L86Q = DFFEAS(A1L86Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[5] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[5]_PORT_A_data_in = A1L161;
C1_q_b[5]_PORT_A_data_in_reg = DFFE(C1_q_b[5]_PORT_A_data_in, C1_q_b[5]_clock_0, , , C1_q_b[5]_clock_enable_0);
C1_q_b[5]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[5]_PORT_A_address_reg = DFFE(C1_q_b[5]_PORT_A_address, C1_q_b[5]_clock_0, , , C1_q_b[5]_clock_enable_0);
C1_q_b[5]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[5]_PORT_B_address_reg = DFFE(C1_q_b[5]_PORT_B_address, C1_q_b[5]_clock_1, , , C1_q_b[5]_clock_enable_1);
C1_q_b[5]_PORT_A_write_enable = VCC;
C1_q_b[5]_PORT_A_write_enable_reg = DFFE(C1_q_b[5]_PORT_A_write_enable, C1_q_b[5]_clock_0, , , C1_q_b[5]_clock_enable_0);
C1_q_b[5]_PORT_B_read_enable = VCC;
C1_q_b[5]_PORT_B_read_enable_reg = DFFE(C1_q_b[5]_PORT_B_read_enable, C1_q_b[5]_clock_1, , , C1_q_b[5]_clock_enable_1);
C1_q_b[5]_clock_0 = gclk;
C1_q_b[5]_clock_1 = gclk;
C1_q_b[5]_clock_enable_0 = A1L98;
C1_q_b[5]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[5]_PORT_B_data_out = MEMORY(C1_q_b[5]_PORT_A_data_in_reg, , C1_q_b[5]_PORT_A_address_reg, C1_q_b[5]_PORT_B_address_reg, C1_q_b[5]_PORT_A_write_enable_reg, C1_q_b[5]_PORT_B_read_enable_reg, , , C1_q_b[5]_clock_0, C1_q_b[5]_clock_1, C1_q_b[5]_clock_enable_0, C1_q_b[5]_clock_enable_1, , );
C1_q_b[5] = C1_q_b[5]_PORT_B_data_out[0];


--A1L87Q is fifomemory~14
--operation mode is normal

A1L87Q_lut_out = A1L161;
A1L87Q = DFFEAS(A1L87Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[6] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[6]_PORT_A_data_in = A1L164;
C1_q_b[6]_PORT_A_data_in_reg = DFFE(C1_q_b[6]_PORT_A_data_in, C1_q_b[6]_clock_0, , , C1_q_b[6]_clock_enable_0);
C1_q_b[6]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[6]_PORT_A_address_reg = DFFE(C1_q_b[6]_PORT_A_address, C1_q_b[6]_clock_0, , , C1_q_b[6]_clock_enable_0);
C1_q_b[6]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[6]_PORT_B_address_reg = DFFE(C1_q_b[6]_PORT_B_address, C1_q_b[6]_clock_1, , , C1_q_b[6]_clock_enable_1);
C1_q_b[6]_PORT_A_write_enable = VCC;
C1_q_b[6]_PORT_A_write_enable_reg = DFFE(C1_q_b[6]_PORT_A_write_enable, C1_q_b[6]_clock_0, , , C1_q_b[6]_clock_enable_0);
C1_q_b[6]_PORT_B_read_enable = VCC;
C1_q_b[6]_PORT_B_read_enable_reg = DFFE(C1_q_b[6]_PORT_B_read_enable, C1_q_b[6]_clock_1, , , C1_q_b[6]_clock_enable_1);
C1_q_b[6]_clock_0 = gclk;
C1_q_b[6]_clock_1 = gclk;
C1_q_b[6]_clock_enable_0 = A1L98;
C1_q_b[6]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[6]_PORT_B_data_out = MEMORY(C1_q_b[6]_PORT_A_data_in_reg, , C1_q_b[6]_PORT_A_address_reg, C1_q_b[6]_PORT_B_address_reg, C1_q_b[6]_PORT_A_write_enable_reg, C1_q_b[6]_PORT_B_read_enable_reg, , , C1_q_b[6]_clock_0, C1_q_b[6]_clock_1, C1_q_b[6]_clock_enable_0, C1_q_b[6]_clock_enable_1, , );
C1_q_b[6] = C1_q_b[6]_PORT_B_data_out[0];


--A1L88Q is fifomemory~16
--operation mode is normal

A1L88Q_lut_out = A1L164;
A1L88Q = DFFEAS(A1L88Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[7] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[7]_PORT_A_data_in = A1L167;
C1_q_b[7]_PORT_A_data_in_reg = DFFE(C1_q_b[7]_PORT_A_data_in, C1_q_b[7]_clock_0, , , C1_q_b[7]_clock_enable_0);
C1_q_b[7]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[7]_PORT_A_address_reg = DFFE(C1_q_b[7]_PORT_A_address, C1_q_b[7]_clock_0, , , C1_q_b[7]_clock_enable_0);
C1_q_b[7]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[7]_PORT_B_address_reg = DFFE(C1_q_b[7]_PORT_B_address, C1_q_b[7]_clock_1, , , C1_q_b[7]_clock_enable_1);
C1_q_b[7]_PORT_A_write_enable = VCC;
C1_q_b[7]_PORT_A_write_enable_reg = DFFE(C1_q_b[7]_PORT_A_write_enable, C1_q_b[7]_clock_0, , , C1_q_b[7]_clock_enable_0);
C1_q_b[7]_PORT_B_read_enable = VCC;
C1_q_b[7]_PORT_B_read_enable_reg = DFFE(C1_q_b[7]_PORT_B_read_enable, C1_q_b[7]_clock_1, , , C1_q_b[7]_clock_enable_1);
C1_q_b[7]_clock_0 = gclk;
C1_q_b[7]_clock_1 = gclk;
C1_q_b[7]_clock_enable_0 = A1L98;
C1_q_b[7]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[7]_PORT_B_data_out = MEMORY(C1_q_b[7]_PORT_A_data_in_reg, , C1_q_b[7]_PORT_A_address_reg, C1_q_b[7]_PORT_B_address_reg, C1_q_b[7]_PORT_A_write_enable_reg, C1_q_b[7]_PORT_B_read_enable_reg, , , C1_q_b[7]_clock_0, C1_q_b[7]_clock_1, C1_q_b[7]_clock_enable_0, C1_q_b[7]_clock_enable_1, , );
C1_q_b[7] = C1_q_b[7]_PORT_B_data_out[0];


--A1L89Q is fifomemory~18
--operation mode is normal

A1L89Q_lut_out = A1L167;
A1L89Q = DFFEAS(A1L89Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[8] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[8]_PORT_A_data_in = A1L170;
C1_q_b[8]_PORT_A_data_in_reg = DFFE(C1_q_b[8]_PORT_A_data_in, C1_q_b[8]_clock_0, , , C1_q_b[8]_clock_enable_0);
C1_q_b[8]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[8]_PORT_A_address_reg = DFFE(C1_q_b[8]_PORT_A_address, C1_q_b[8]_clock_0, , , C1_q_b[8]_clock_enable_0);
C1_q_b[8]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[8]_PORT_B_address_reg = DFFE(C1_q_b[8]_PORT_B_address, C1_q_b[8]_clock_1, , , C1_q_b[8]_clock_enable_1);
C1_q_b[8]_PORT_A_write_enable = VCC;
C1_q_b[8]_PORT_A_write_enable_reg = DFFE(C1_q_b[8]_PORT_A_write_enable, C1_q_b[8]_clock_0, , , C1_q_b[8]_clock_enable_0);
C1_q_b[8]_PORT_B_read_enable = VCC;
C1_q_b[8]_PORT_B_read_enable_reg = DFFE(C1_q_b[8]_PORT_B_read_enable, C1_q_b[8]_clock_1, , , C1_q_b[8]_clock_enable_1);
C1_q_b[8]_clock_0 = gclk;
C1_q_b[8]_clock_1 = gclk;
C1_q_b[8]_clock_enable_0 = A1L98;
C1_q_b[8]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[8]_PORT_B_data_out = MEMORY(C1_q_b[8]_PORT_A_data_in_reg, , C1_q_b[8]_PORT_A_address_reg, C1_q_b[8]_PORT_B_address_reg, C1_q_b[8]_PORT_A_write_enable_reg, C1_q_b[8]_PORT_B_read_enable_reg, , , C1_q_b[8]_clock_0, C1_q_b[8]_clock_1, C1_q_b[8]_clock_enable_0, C1_q_b[8]_clock_enable_1, , );
C1_q_b[8] = C1_q_b[8]_PORT_B_data_out[0];


--A1L90Q is fifomemory~20
--operation mode is normal

A1L90Q_lut_out = A1L170;
A1L90Q = DFFEAS(A1L90Q_lut_out, gclk, VCC, , A1L102, , , , );


--C1_q_b[9] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[9]_PORT_A_data_in = A1L173;
C1_q_b[9]_PORT_A_data_in_reg = DFFE(C1_q_b[9]_PORT_A_data_in, C1_q_b[9]_clock_0, , , C1_q_b[9]_clock_enable_0);
C1_q_b[9]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[9]_PORT_A_address_reg = DFFE(C1_q_b[9]_PORT_A_address, C1_q_b[9]_clock_0, , , C1_q_b[9]_clock_enable_0);
C1_q_b[9]_PORT_B_address = BUS(A1L32, A1L29, A1L41, A1L38, A1L50, A1L35, A1L44, A1L26, A1L47, A1L23);
C1_q_b[9]_PORT_B_address_reg = DFFE(C1_q_b[9]_PORT_B_address, C1_q_b[9]_clock_1, , , C1_q_b[9]_clock_enable_1);
C1_q_b[9]_PORT_A_write_enable = VCC;
C1_q_b[9]_PORT_A_write_enable_reg = DFFE(C1_q_b[9]_PORT_A_write_enable, C1_q_b[9]_clock_0, , , C1_q_b[9]_clock_enable_0);
C1_q_b[9]_PORT_B_read_enable = VCC;
C1_q_b[9]_PORT_B_read_enable_reg = DFFE(C1_q_b[9]_PORT_B_read_enable, C1_q_b[9]_clock_1, , , C1_q_b[9]_clock_enable_1);
C1_q_b[9]_clock_0 = gclk;
C1_q_b[9]_clock_1 = gclk;
C1_q_b[9]_clock_enable_0 = A1L98;
C1_q_b[9]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[9]_PORT_B_data_out = MEMORY(C1_q_b[9]_PORT_A_data_in_reg, , C1_q_b[9]_PORT_A_address_reg, C1_q_b[9]_PORT_B_address_reg, C1_q_b[9]_PORT_A_write_enable_reg, C1_q_b[9]_PORT_B_read_enable_reg, , , C1_q_b[9]_clock_0, C1_q_b[9]_clock_1, C1_q_b[9]_clock_enable_0, C1_q_b[9]_clock_enable_1, , );
C1_q_b[9] = C1_q_b[9]_PORT_B_data_out[0];


--A1L91Q is fifomemory~22
--operation mode is normal

A1L91Q_lut_out = A1L173;
A1L91Q = DFFEAS(A1L91Q_lut_out, gclk, VCC, , A1L102, , , , );