usb_fpga.fit.rpt

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

; Router Timing Optimization Level                     ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                          ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                             ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                 ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                          ; Off                            ; Off                            ;
; Optimize Timing                                      ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing           ; On                             ; On                             ;
; Limit to One Fitting Attempt                         ; Off                            ; Off                            ;
; Final Placement Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations          ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                        ; 1                              ; 1                              ;
; Slow Slew Rate                                       ; Off                            ; Off                            ;
; PCI I/O                                              ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                            ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                     ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic   ; Off                            ; Off                            ;
; Perform Register Duplication                         ; Off                            ; Off                            ;
; Perform Register Retiming                            ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining               ; Off                            ; Off                            ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication             ; Auto                           ; Auto                           ;
; Auto Register Duplication                            ; Off                            ; Off                            ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; Reserve ASDO pin after configuration.        ; As input tri-stated ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.pin.


+------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                          ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 134 / 5,980 ( 2 % )      ;
;     -- Combinational with no register       ; 62                       ;
;     -- Register only                        ; 32                       ;
;     -- Combinational with a register        ; 40                       ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 24                       ;
;     -- 3 input functions                    ; 50                       ;
;     -- 2 input functions                    ; 23                       ;
;     -- 1 input functions                    ; 17                       ;
;     -- 0 input functions                    ; 20                       ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 97                       ;
;     -- arithmetic mode                      ; 37                       ;
;     -- qfbk mode                            ; 1                        ;
;     -- register cascade mode                ; 0                        ;
;     -- synchronous clear/load mode          ; 29                       ;
;     -- asynchronous clear/load mode         ; 23                       ;
;                                             ;                          ;
; Total LABs                                  ; 26 / 598 ( 4 % )         ;