usb_fpga.map.rpt

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

; WIDTH_BYTEENA_A                    ; 1               ; Untyped               ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped               ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped               ;
; BYTE_SIZE                          ; 8               ; Untyped               ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped               ;
; INIT_FILE                          ; UNUSED          ; Untyped               ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped               ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped               ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped               ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped               ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped               ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped               ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped               ;
; CBXI_PARAMETER                     ; altsyncram_lk81 ; Untyped               ;
+------------------------------------+-----------------+-----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Tue Oct 30 20:34:29 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USB_FPGA -c USB_FPGA
Info: Found 2 design units, including 1 entities, in source file USB_FPGA.vhd
    Info: Found design unit 1: USB_FPGA-ARC_USB_FPGA
    Info: Found entity 1: USB_FPGA
Info: Elaborating entity "USB_FPGA" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at USB_FPGA.vhd(70): object "rden" declared but not used
Info (10035): Verilog HDL or VHDL information at USB_FPGA.vhd(70): object "wren" declared but not used
Warning (10034): Output port "RDY2" at USB_FPGA.vhd(33) has no driver
Warning (10034): Output port "RDY3" at USB_FPGA.vhd(34) has no driver
Warning (10034): Output port "RDY4" at USB_FPGA.vhd(35) has no driver
Warning (10034): Output port "RDY5" at USB_FPGA.vhd(36) has no driver
Warning (10034): Output port "SRAMFD[15]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[14]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[13]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[12]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[11]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[10]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[9]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[8]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[7]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[6]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[5]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[4]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[3]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[2]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[1]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMFD[0]" at USB_FPGA.vhd(38) has no driver
Warning (10034): Output port "SRAMWE" at USB_FPGA.vhd(40) has no driver
Warning (10034): Output port "SRAMCE" at USB_FPGA.vhd(41) has no driver
Warning (10034): Output port "SRAMOE" at USB_FPGA.vhd(42) has no driver
Warning (10034): Output port "SRAMUB" at USB_FPGA.vhd(43) has no driver
Warning (10034): Output port "SRAMLB" at USB_FPGA.vhd(44) has no driver
Info: Duplicate registers merged to single register
    Info: Duplicate register "process1~21" merged to single register "process1~0"
    Info: Duplicate register "process1~19" merged to single register "process1~0"
    Info: Duplicate register "process1~17" merged to single register "process1~0"
    Info: Duplicate register "process1~15" merged to single register "process1~0"
    Info: Duplicate register "process1~13" merged to single register "process1~0"
    Info: Duplicate register "process1~11" merged to single register "process1~0"
    Info: Duplicate register "process1~9" merged to single register "process1~0"
    Info: Duplicate register "process1~7" merged to single register "process1~0"
    Info: Duplicate register "process1~5" merged to single register "process1~0"
    Info: Duplicate register "process1~3" merged to single register "process1~0"
    Info: Duplicate register "process1~1" merged to single register "process1~0"
    Info: Duplicate register "process1~23" merged to single register "process1~0"
    Info: Duplicate register "process1~25" merged to single register "process1~0"
    Info: Duplicate register "process1~29" merged to single register "process1~0"
    Info: Duplicate register "process1~27" merged to single register "process1~0"
Warning: Created node "fifomemory~1" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design.
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altsyncram megafunction (NUMWORDS_A=1024, WIDTH_A=16) from the following design logic: "fifomemory~1"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lk81.tdf
    Info: Found entity 1: altsyncram_lk81
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "RDY2" stuck at GND
    Warning: Pin "RDY3" stuck at GND
    Warning: Pin "RDY4" stuck at GND
    Warning: Pin "RDY5" stuck at GND
    Warning: Pin "SRAMFD[0]" stuck at GND
    Warning: Pin "SRAMFD[1]" stuck at GND
    Warning: Pin "SRAMFD[2]" stuck at GND
    Warning: Pin "SRAMFD[3]" stuck at GND
    Warning: Pin "SRAMFD[4]" stuck at GND
    Warning: Pin "SRAMFD[5]" stuck at GND
    Warning: Pin "SRAMFD[6]" stuck at GND
    Warning: Pin "SRAMFD[7]" stuck at GND
    Warning: Pin "SRAMFD[8]" stuck at GND
    Warning: Pin "SRAMFD[9]" stuck at GND
    Warning: Pin "SRAMFD[10]" stuck at GND
    Warning: Pin "SRAMFD[11]" stuck at GND
    Warning: Pin "SRAMFD[12]" stuck at GND
    Warning: Pin "SRAMFD[13]" stuck at GND
    Warning: Pin "SRAMFD[14]" stuck at GND
    Warning: Pin "SRAMFD[15]" stuck at GND
    Warning: Pin "SRAMADR[9]" stuck at GND
    Warning: Pin "SRAMADR[10]" stuck at GND
    Warning: Pin "SRAMADR[11]" stuck at GND
    Warning: Pin "SRAMADR[12]" stuck at GND
    Warning: Pin "SRAMADR[13]" stuck at GND
    Warning: Pin "SRAMADR[14]" stuck at GND
    Warning: Pin "SRAMADR[15]" stuck at GND
    Warning: Pin "SRAMADR[16]" stuck at GND
    Warning: Pin "SRAMADR[17]" stuck at GND
    Warning: Pin "SRAMWE" stuck at GND
    Warning: Pin "SRAMCE" stuck at GND
    Warning: Pin "SRAMOE" stuck at GND
    Warning: Pin "SRAMUB" stuck at GND
    Warning: Pin "SRAMLB" stuck at GND
Info: Registers with preset signals will power-up high
Warning: Design contains 5 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CTL3"
    Warning: No output dependent on input pin "CTL4"
    Warning: No output dependent on input pin "CTL5"
    Warning: No output dependent on input pin "KEY2"
    Warning: No output dependent on input pin "KEY4"
Info: Implemented 246 device resources after synthesis - the final resource count might be different
    Info: Implemented 21 input pins
    Info: Implemented 49 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 144 logic cells
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 67 warnings
    Info: Processing ended: Tue Oct 30 20:34:36 2007
    Info: Elapsed time: 00:00:08