usb_fpga.fit.talkback.xml

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

	</row>
	<row>
		<name>LED2</name>
		<pin__>140</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>8</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>LED3</name>
		<pin__>139</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>7</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>LED4</name>
		<pin__>138</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>7</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>RDY0_SLRD</name>
		<pin__>179</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>20</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>RDY1_SLWR</name>
		<pin__>178</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>19</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>RDY2</name>
		<pin__>177</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>19</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>RDY3</name>
		<pin__>176</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>19</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>RDY4</name>
		<pin__>175</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>18</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>RDY5</name>
		<pin__>174</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>18</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[0]</name>
		<pin__>237</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>4</x_coordinate>
		<y_coordinate>21</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[10]</name>
		<pin__>38</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>8</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[11]</name>
		<pin__>60</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>1</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[12]</name>
		<pin__>160</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[13]</name>
		<pin__>105</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>28</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[14]</name>
		<pin__>195</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>28</x_coordinate>
		<y_coordinate>21</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[15]</name>
		<pin__>50</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[16]</name>
		<pin__>85</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>14</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[17]</name>
		<pin__>170</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>35</x_coordinate>
		<y_coordinate>17</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
		<load>Unspecified</load>
	</row>
	<row>
		<name>SRAMADR[1]</name>