usb_fpga.tan.talkback.xml

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

<!--
This XML file (created on Tue Oct 30 20:35:04 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000fea1dae48</host_id>
	<nic_id>000fea1dae48</nic_id>
	<cdrive_id>24a001f3</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Tue Oct 30 20:35:05 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">3000</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<top_file>G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off USB_FPGA -c USB_FPGA --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Tue Oct 30 20:35:04 2007</info>
	<info>Info: th for register &quot;FX2FD[7]~reg0&quot; (data pin = &quot;RESETFPGA&quot;, clock pin = &quot;gclk&quot;) is -0.704 ns</info>
	<info>Info: - Shortest pin to register delay is 3.673 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>gclk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>10.108 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>15.702 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tpd</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>11.567 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>-0.704 ns</actual>
	</nonclk>
	<clk>
		<name>gclk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>121.92 MHz ( period = 8.202 ns )</actual>
	</clk>
</performance>
<compile_id>66648C68</compile_id>
</talkback>