jkdl.vhd

变频器移相控制

--**********************************************************  
--  jkdl  :  接口电路 
--  Din   :  数据或指令先发最低位    ADD0 ---- ADD7 
--  Dout  :  数据先输出最低位        DB0  ---- DB7   
--  CS    :  '0' 选中
--  CLK   :  上升沿有效

------------------        数据格式      --------------------
--  Din   :  ADD0----ADD7  X  DB0----DB7  X
--  ADD   :  XXX R/W X D2--D0   
--  R/W   :  '0' 写   '1' 读
------------------------------------------------------------

--  czp_clk :  当写指令时发送脉冲
--  czp_q8  : 
--  czp_q16 : 
--  pzc     :

--**********************************************************

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY jkdl IS
   PORT( CS      : IN std_logic; 
         CLK     : IN std_logic;          
         Din     : IN std_logic;                                
         Dout    : OUT std_logic; 
         
         
         czp_clk : OUT std_logic; 
         czp_q8  : OUT std_logic_vector(7 downto 0);
         czp_q16 : OUT std_logic_vector(7 downto 0);
         pzc     : IN  std_logic_vector(7 downto 0);
         kg_temp : OUT std_logic_vector(3 downto 0)   ------
         );            
END jkdl; 


ARCHITECTURE jkdl_A OF jkdl IS  

   SIGNAL  Q_j8        : std_logic;  
   SIGNAL  CLk_d       : std_logic;
   SIGNAL  Q_j16       : std_logic;  
   SIGNAL  Q_j17       : std_logic;  
   SIGNAL  CS_temp     : std_logic;  
   SIGNAL  pzc_cs      : std_logic;   
   SIGNAL  js_temp     : std_logic_vector(4 downto 0);
   SIGNAL  jsk_temp    : std_logic_vector(3 downto 0);  
   SIGNAL  czp_q8_t    : std_logic_vector(7 downto 0);  
   SIGNAL  czp_q8_t1   : std_logic_vector(7 downto 0);  
   SIGNAL  czp_q16_t   : std_logic_vector(7 downto 0);   
   SIGNAL  pzc_temp    : std_logic_vector(7 downto 0);  
BEGIN

P1:  PROCESS(CS,js_temp,CLK)                                      
     BEGIN
        IF CS='1'  THEN 
           js_temp <="00000";
        ELSIF (CLK'EVENT) and (CLK='1') THEN                  
              js_temp <= js_temp+1;                                          
        END IF;
     END PROCESS; 

     
P2:  PROCESS(js_temp) 
     BEGIN
        CASE js_temp IS
           WHEN "00000" => jsk_temp <= "1000" ;      --  0
           WHEN "00001" => jsk_temp <= "1000" ;      
           WHEN "00010" => jsk_temp <= "1000" ;    
           WHEN "00011" => jsk_temp <= "1000" ;            
           WHEN "00100" => jsk_temp <= "1000" ;     
           WHEN "00101" => jsk_temp <= "1000" ;      
           WHEN "00110" => jsk_temp <= "1000" ;    
           WHEN "00111" => jsk_temp <= "1000" ;            
           WHEN "01000" => jsk_temp <= "0100" ;      --  8  
               
           WHEN "01001" => jsk_temp <= "0000" ;      --  9 
           WHEN "01010" => jsk_temp <= "0010" ;    
           WHEN "01011" => jsk_temp <= "0010" ;            
           WHEN "01100" => jsk_temp <= "0010" ;     
           WHEN "01101" => jsk_temp <= "0010" ;      
           WHEN "01110" => jsk_temp <= "0010" ;    
           WHEN "01111" => jsk_temp <= "0010" ;             
           WHEN "10000" => jsk_temp <= "0010" ;      --  16         
           WHEN "10001" => jsk_temp <= "0010" ;      
           WHEN "10010" => jsk_temp <= "0001" ;      --  18
     
           WHEN OTHERS  => jsk_temp <= "XXXX" ;
        END CASE;
     END PROCESS;  
  

     kg_temp <= jsk_temp;   --

     CS_temp <=NOT CS;
     Q_j8 <=jsk_temp(3) AND CS_temp;            
     Q_j16 <=jsk_temp(1) AND CS_temp; 
     Q_j17 <=jsk_temp(0) AND (NOT czp_q8_t1(4));   --   XXX R/W XXXX
     pzc_cs <= jsk_temp(1) AND CS_temp AND czp_q8_t1(4);
         
     
P3:   PROCESS(Q_j8,CLK,Din)                     
      BEGIN
         IF Q_j8='1' THEN
           IF (CLK'EVENT) and (CLK='1') THEN   --上升沿
              czp_q8_t(7)<=Din;
              czp_q8_t(6)<=czp_q8_t(7);
              czp_q8_t(5)<=czp_q8_t(6);
              czp_q8_t(4)<=czp_q8_t(5);
              czp_q8_t(3)<=czp_q8_t(4);
              czp_q8_t(2)<=czp_q8_t(3);
              czp_q8_t(1)<=czp_q8_t(2);
              czp_q8_t(0)<=czp_q8_t(1);   
           END IF;   
         END IF;
      END PROCESS;
    

      CLk_d <= jsk_temp(2) AND CLK;
P4:   PROCESS(CLk_d)                        --   8                   
      BEGIN 
         IF (CLk_d'EVENT) and (CLk_d='0') THEN   --  下降沿
            czp_q8_t1<=czp_q8_t;
              
         END IF;
      END PROCESS;     
      czp_q8<=czp_q8_t1;

P5:   PROCESS(Q_j16,CLK,Din)                     
      BEGIN
         IF Q_j16='1' THEN
           IF (CLK'EVENT) and (CLK='0') THEN   
              czp_q16_t(7)<=Din;
              czp_q16_t(6)<=czp_q16_t(7);
              czp_q16_t(5)<=czp_q16_t(6);
              czp_q16_t(4)<=czp_q16_t(5);
              czp_q16_t(3)<=czp_q16_t(4);
              czp_q16_t(2)<=czp_q16_t(3);
              czp_q16_t(1)<=czp_q16_t(2);
              czp_q16_t(0)<=czp_q16_t(1);
   
           END IF;   
         END IF;
      END PROCESS;

--P6:   PROCESS(Q_j17)                             --  R/W : 0                
--      BEGIN 
--         IF (Q_j17'EVENT) and (Q_j17='1') THEN   --上升沿
--            czp_q16<=czp_q16_t;
               
--         END IF;
--      END PROCESS;
      czp_clk <= Q_j17;
      czp_q16<=czp_q16_t;

     -- pzc_temp <= pzc; 
P8:   PROCESS(pzc_cs,CLK)                     
      BEGIN
         IF (CLK'EVENT) and (CLK='0') THEN   -------------
            IF pzc_cs='0' THEN
               pzc_temp <= pzc;
            ELSE    
               pzc_temp(6)<=pzc_temp(7);
               pzc_temp(5)<=pzc_temp(6);
               pzc_temp(4)<=pzc_temp(5);
               pzc_temp(3)<=pzc_temp(4);
               pzc_temp(2)<=pzc_temp(3);
               pzc_temp(1)<=pzc_temp(2);
               pzc_temp(0)<=pzc_temp(1); 
               Dout <= pzc_temp(0); 
            END IF; 
         END IF;
      END PROCESS;
       
         
END jkdl_A;