📄 pulse_drive.rpt
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Total I/O pins used: 28/64 ( 43%)
Total logic cells used: 103/128 ( 80%)
Total shareable expanders used: 5/128 ( 3%)
Total Turbo logic cells used: 103/128 ( 80%)
Total shareable expanders not available (n/a): 13/128 ( 10%)
Average fan-in: 8.43
Total fan-in: 869
Total input pins required: 18
Total fast input logic cells required: 0
Total output pins required: 8
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 103
Total flipflops required: 92
Total product terms required: 275
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 3/ 128 ( 2%)
Device-Specific Information: e:\can-drive\pulse_drive.rpt
pulse_drive
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 CLK
29 (38) (C) INPUT 0 0 0 0 0 0 1 HALF_US
22 (17) (B) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT0
20 (21) (B) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT1
21 (19) (B) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT2
4 (16) (A) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT3
5 (14) (A) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT4
6 (13) (A) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT5
8 (11) (A) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT6
9 (8) (A) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT7
10 (6) (A) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT8
11 (5) (A) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT9
31 (35) (C) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT10
17 (25) (B) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT11
16 (27) (B) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT12
15 (29) (B) INPUT 0 0 0 0 0 0 1 PULSE_SHIFT13
12 (3) (A) INPUT 0 0 0 0 0 0 32 RESET
2 - - INPUT G 0 0 0 0 0 0 18 VOL_LATCH
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\can-drive\pulse_drive.rpt
pulse_drive
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
57 88 F FF t 0 0 0 0 6 0 0 T1_LED
46 69 E FF t 0 0 0 0 7 2 5 T1 (:80)
45 67 E FF t 0 0 0 0 6 0 0 T2_LED
48 72 E FF t 0 0 0 0 7 2 5 T2 (:82)
39 53 D FF t 0 0 0 0 6 0 0 T3_LED
36 57 D FF t 0 0 0 0 7 2 5 T3 (:79)
18 24 B FF t 0 0 0 0 6 0 0 T4_LED
37 56 D FF t 0 0 0 0 7 2 5 T4 (:81)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\can-drive\pulse_drive.rpt
pulse_drive
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(73) 115 H LCELL t 0 0 0 0 7 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder0|result_node6
- 114 H LCELL t 0 0 0 0 8 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder0|result_node7
(79) 125 H LCELL t ! 0 0 0 0 9 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder1|result_node0
- 124 H LCELL t 0 0 0 0 10 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder1|result_node1
(81) 128 H LCELL t 0 0 0 0 11 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder1|result_node2
- 116 H LCELL t 0 0 0 0 12 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder1|result_node3
(75) 118 H LCELL t 0 0 0 0 13 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder1|result_node4
- 119 H LCELL t 0 0 0 0 14 0 1 |LPM_ADD_SUB:879|addcore:adder|addcore:adder1|result_node5
- 113 H TFFE + t 0 0 0 1 14 0 19 QA14 (:31)
(56) 86 F TFFE + t 0 0 0 1 13 0 19 QA13 (:32)
(63) 97 G TFFE + t 0 0 0 1 12 0 20 QA12 (:33)
- 98 G TFFE + t 0 0 0 1 11 0 21 QA11 (:34)
(64) 99 G TFFE + t 0 0 0 1 10 0 22 QA10 (:35)
- 100 G TFFE + t 0 0 0 1 9 0 23 QA9 (:36)
(65) 101 G TFFE + t 0 0 0 1 8 0 24 QA8 (:37)
(71) 112 G TFFE + t 0 0 0 1 7 0 25 QA7 (:38)
(70) 109 G TFFE + t 0 0 0 1 6 0 26 QA6 (:39)
- 89 F TFFE + t 0 0 0 1 5 0 27 QA5 (:40)
- 81 F TFFE + t 0 0 0 1 4 0 28 QA4 (:41)
- 90 F TFFE + t 0 0 0 1 3 0 29 QA3 (:42)
(58) 91 F TFFE + t 0 0 0 1 2 0 30 QA2 (:43)
(60) 93 F TFFE + t 0 0 0 1 1 0 31 QA1 (:44)
(61) 94 F TFFE + t 0 0 0 1 0 0 32 QA0 (:45)
(74) 117 H DFFE + t 1 0 0 2 30 0 2 QB14 (:46)
- 110 G DFFE + t 0 0 0 2 17 0 2 QB13 (:47)
- 108 G DFFE + t 0 0 0 2 17 0 3 QB12 (:48)
(69) 107 G DFFE + t 0 0 0 2 17 0 4 QB11 (:49)
- 102 G DFFE + t 0 0 0 2 17 0 5 QB10 (:50)
(22) 17 B DFFE + t 0 0 0 2 17 0 6 QB9 (:51)
- 103 G DFFE + t 0 0 0 2 17 0 7 QB8 (:52)
(54) 83 F DFFE + t 0 0 0 2 17 0 8 QB7 (:53)
(55) 85 F DFFE + t 0 0 0 2 17 0 9 QB6 (:54)
(12) 3 A DFFE + t 2 0 1 2 23 0 11 QB5 (:55)
- 12 A DFFE + t 1 0 0 2 22 0 13 QB4 (:56)
- 95 F DFFE + t 0 0 0 2 17 0 14 QB3 (:57)
- 2 A DFFE + t 2 1 1 2 19 0 15 QB2 (:58)
- 106 G DFFE + t 1 1 0 2 18 0 16 QB1 (:59)
(68) 105 G TFFE + t 0 0 0 2 17 0 16 QB0 (:60)
- 84 F DFFE + t 0 0 0 1 1 2 8 CAY (:61)
- 121 H DFFE + t 0 0 0 1 1 2 8 CBY (:62)
(27) 43 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT13 (:64)
- 41 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT12 (:65)
- 42 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT11 (:66)
(30) 37 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT10 (:67)
- 39 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT9 (:68)
(24) 46 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT8 (:69)
(28) 40 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT7 (:70)
(29) 38 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT6 (:71)
(31) 35 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT5 (:72)
- 34 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT4 (:73)
- 44 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT3 (:74)
(23) 48 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT2 (:75)
- 47 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT1 (:76)
(25) 45 C DFFE + t 0 0 0 1 0 0 1 VOL_SHIFT0 (:77)
- 33 C TFFE t 0 0 0 0 1 4 16 TWO_US (:78)
- 22 B TFFE t 0 0 0 1 0 0 1 US_CLK (:83)
(80) 126 H OR2 s t 1 0 1 1 20 0 1 ~973~1
(77) 123 H OR2 s t 1 0 1 1 20 0 1 ~979~1
- 122 H OR2 s t 1 0 1 1 19 0 1 ~985~1
- 50 D DFFE t 1 0 1 0 6 1 1 DT_COUNTER3 (:1300)
- 58 D DFFE t 0 0 0 0 5 1 2 DT_COUNTER2 (:1301)
- 55 D DFFE t 0 0 0 0 4 1 3 DT_COUNTER1 (:1302)
- 54 D DFFE t 0 0 0 0 3 1 4 DT_COUNTER0 (:1303)
(50) 75 E DFFE t 1 0 1 0 6 1 1 DT_COUNTER3~604 (:1405)
(49) 73 E DFFE t 0 0 0 0 5 1 2 DT_COUNTER2~604 (:1406)
- 71 E DFFE t 0 0 0 0 4 1 3 DT_COUNTER1~604 (:1407)
- 70 E DFFE t 0 0 0 0 3 1 4 DT_COUNTER0~604 (:1408)
- 52 D DFFE t 1 0 1 0 6 1 1 DT_COUNTER3~703 (:1510)
(40) 51 D DFFE t 0 0 0 0 5 1 2 DT_COUNTER2~703 (:1511)
(41) 49 D DFFE t 0 0 0 0 4 1 3 DT_COUNTER1~703 (:1512)
(33) 64 D DFFE t 0 0 0 0 3 1 4 DT_COUNTER0~703 (:1513)
(52) 80 E DFFE t 1 0 1 0 6 1 1 DT_COUNTER3~802 (:1616)
- 79 E DFFE t 0 0 0 0 5 1 2 DT_COUNTER2~802 (:1617)
- 78 E DFFE t 0 0 0 0 4 1 3 DT_COUNTER1~802 (:1618)
- 76 E DFFE t 0 0 0 0 3 1 4 DT_COUNTER0~802 (:1619)
(62) 96 F DFFE t 1 0 1 0 6 1 1 LED_COUNTER4 (:1760)
- 92 F TFFE t 0 0 0 0 4 1 1 LED_COUNTER3 (:1761)
- 87 F TFFE t 0 0 0 0 3 1 2 LED_COUNTER2 (:1762)
- 82 F TFFE t 0 0 0 0 2 1 3 LED_COUNTER1 (:1763)
- 36 C TFFE t 0 0 0 0 1 1 4 LED_COUNTER0 (:1764)
(51) 77 E DFFE t 1 0 1 0 6 1 1 LED_COUNTER4~1022 (:1861)
(44) 65 E TFFE t 0 0 0 0 4 1 1 LED_COUNTER3~1022 (:1862)
- 66 E TFFE t 0 0 0 0 3 1 2 LED_COUNTER2~1022 (:1863)
- 68 E TFFE t 0 0 0 0 2 1 3 LED_COUNTER1~1022 (:1864)
- 74 E TFFE t 0 0 0 0 1 1 4 LED_COUNTER0~1022 (:1865)
(35) 59 D DFFE t 1 0 1 0 6 1 1 LED_COUNTER4~1096 (:1962)
- 60 D TFFE t 0 0 0 0 4 1 1 LED_COUNTER3~1096 (:1963)
(34) 61 D TFFE t 0 0 0 0 3 1 2 LED_COUNTER2~1096 (:1964)
- 62 D TFFE t 0 0 0 0 2 1 3 LED_COUNTER1~1096 (:1965)
- 63 D TFFE t 0 0 0 0 1 1 4 LED_COUNTER0~1096 (:1966)
(14) 32 B DFFE t 1 0 1 0 6 1 1 LED_COUNTER4~1170 (:2063)
- 18 B TFFE t 0 0 0 0 4 1 1 LED_COUNTER3~1170 (:2064)
(21) 19 B TFFE t 0 0 0 0 3 1 2 LED_COUNTER2~1170 (:2065)
- 20 B TFFE t 0 0 0 0 2 1 3 LED_COUNTER1~1170 (:2066)
(20) 21 B TFFE t 0 0 0 0 1 1 4 LED_COUNTER0~1170 (:2067)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\can-drive\pulse_drive.rpt
pulse_drive
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC3 QB5
| +--- LC12 QB4
| | +- LC2 QB2
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC3 -> * - - | * - - - - - - * | <-- QB5
LC12 -> * * - | * - - - - - - * | <-- QB4
LC2 -> * * * | * - - - - - - * | <-- QB2
Pin
83 -> - - - | - - - - - - - - | <-- CLK
12 -> * * * | * * - - - * * * | <-- RESET
2 -> * * * | * * - - - * * * | <-- VOL_LATCH
LC113-> * * * | * * - - - * * * | <-- QA14
LC86 -> * * * | * * - - - * * * | <-- QA13
LC97 -> * * * | * * - - - * * * | <-- QA12
LC98 -> * * * | * * - - - * * * | <-- QA11
LC99 -> * * * | * * - - - * * * | <-- QA10
LC100-> * * * | * * - - - * * * | <-- QA9
LC101-> * * * | * * - - - * * * | <-- QA8
LC112-> * * * | * * - - - * * * | <-- QA7
LC109-> * * * | * * - - - * * * | <-- QA6
LC89 -> * * * | * * - - - * * * | <-- QA5
LC81 -> * * * | * * - - - * * * | <-- QA4
LC90 -> * * * | * * - - - * * * | <-- QA3
LC91 -> * * * | * * - - - * * * | <-- QA2
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