📄 pulse_drive.rpt
字号:
Project Information e:\can-drive\pulse_drive.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 07/17/2007 17:11:09
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
PULSE_DRIVE
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
pulse_drive
EPM7128SLC84-6 18 8 0 103 5 80 %
User Pins: 18 8 0
Project Information e:\can-drive\pulse_drive.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Line 73: File e:\can-drive\pulse_drive.vhd: Subtype 1 (ASCENDING) has different direction than subtype 2 (DESCENDING)
Warning: Line 73: File e:\can-drive\pulse_drive.vhd: Subtype 1 (ASCENDING) has different direction than subtype 2 (DESCENDING)
Project Information e:\can-drive\pulse_drive.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK' chosen for auto global Clock
INFO: Signal 'VOL_LATCH' chosen for auto global Clock
Project Information e:\can-drive\pulse_drive.rpt
** FILE HIERARCHY **
|lpm_add_sub:211|
|lpm_add_sub:211|addcore:adder|
|lpm_add_sub:211|addcore:adder|addcore:adder1|
|lpm_add_sub:211|addcore:adder|addcore:adder0|
|lpm_add_sub:211|altshift:result_ext_latency_ffs|
|lpm_add_sub:211|altshift:carry_ext_latency_ffs|
|lpm_add_sub:211|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:561|
|lpm_add_sub:561|addcore:adder|
|lpm_add_sub:561|addcore:adder|addcore:adder1|
|lpm_add_sub:561|addcore:adder|addcore:adder0|
|lpm_add_sub:561|altshift:result_ext_latency_ffs|
|lpm_add_sub:561|altshift:carry_ext_latency_ffs|
|lpm_add_sub:561|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:879|
|lpm_add_sub:879|addcore:adder|
|lpm_add_sub:879|addcore:adder|addcore:adder1|
|lpm_add_sub:879|addcore:adder|addcore:adder0|
|lpm_add_sub:879|altshift:result_ext_latency_ffs|
|lpm_add_sub:879|altshift:carry_ext_latency_ffs|
|lpm_add_sub:879|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1323|
|lpm_add_sub:1323|addcore:adder|
|lpm_add_sub:1323|addcore:adder|addcore:adder0|
|lpm_add_sub:1323|altshift:result_ext_latency_ffs|
|lpm_add_sub:1323|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1323|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1428|
|lpm_add_sub:1428|addcore:adder|
|lpm_add_sub:1428|addcore:adder|addcore:adder0|
|lpm_add_sub:1428|altshift:result_ext_latency_ffs|
|lpm_add_sub:1428|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1428|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1534|
|lpm_add_sub:1534|addcore:adder|
|lpm_add_sub:1534|addcore:adder|addcore:adder0|
|lpm_add_sub:1534|altshift:result_ext_latency_ffs|
|lpm_add_sub:1534|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1534|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1640|
|lpm_add_sub:1640|addcore:adder|
|lpm_add_sub:1640|addcore:adder|addcore:adder0|
|lpm_add_sub:1640|altshift:result_ext_latency_ffs|
|lpm_add_sub:1640|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1640|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1782|
|lpm_add_sub:1782|addcore:adder|
|lpm_add_sub:1782|addcore:adder|addcore:adder0|
|lpm_add_sub:1782|altshift:result_ext_latency_ffs|
|lpm_add_sub:1782|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1782|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1883|
|lpm_add_sub:1883|addcore:adder|
|lpm_add_sub:1883|addcore:adder|addcore:adder0|
|lpm_add_sub:1883|altshift:result_ext_latency_ffs|
|lpm_add_sub:1883|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1883|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1984|
|lpm_add_sub:1984|addcore:adder|
|lpm_add_sub:1984|addcore:adder|addcore:adder0|
|lpm_add_sub:1984|altshift:result_ext_latency_ffs|
|lpm_add_sub:1984|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1984|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2085|
|lpm_add_sub:2085|addcore:adder|
|lpm_add_sub:2085|addcore:adder|addcore:adder0|
|lpm_add_sub:2085|altshift:result_ext_latency_ffs|
|lpm_add_sub:2085|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2085|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\can-drive\pulse_drive.rpt
pulse_drive
***** Logic for device 'pulse_drive' compiled without errors.
Device: EPM7128SLC84-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
P P P P P P P
U U U U U U U
L L L L L L L
S S S S S S S V
E E E E E E E O R R R R R R
_ _ _ _ _ _ _ L E E E E E E
S S S S S S S V _ S S S S S S
H H H H H H H C L E E E V E E E
I I I I I I I C A R R R C R R R
F F F F G F F F I T G G C G V V V C V V V
T T T T N T T T N C N N L N E E E I E E E
9 8 7 6 D 5 4 3 T H D D K D D D D O D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
RESET | 12 74 | RESERVED
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
PULSE_SHIFT13 | 15 71 | #TDO
PULSE_SHIFT12 | 16 70 | RESERVED
PULSE_SHIFT11 | 17 69 | RESERVED
T4_LED | 18 68 | RESERVED
GND | 19 67 | RESERVED
PULSE_SHIFT1 | 20 66 | VCCIO
PULSE_SHIFT2 | 21 65 | RESERVED
PULSE_SHIFT0 | 22 EPM7128SLC84-6 64 | RESERVED
#TMS | 23 63 | RESERVED
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
RESERVED | 28 58 | RESERVED
HALF_US | 29 57 | T1_LED
RESERVED | 30 56 | RESERVED
PULSE_SHIFT10 | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R T T V T R R G V R T T G T R R R R V
E E E 3 4 C 3 E E N C E 2 1 N 2 E E E E C
S S S C _ S S D C S _ D S S S S C
E E E I L E E I E L E E E E I
R R R O E R R N R E R R R R O
V V V D V V T V D V V V V
E E E E E E E E E E
D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\can-drive\pulse_drive.rpt
pulse_drive
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 8/ 8(100%) 5/16( 31%) 28/36( 77%)
B: LC17 - LC32 8/16( 50%) 8/ 8(100%) 1/16( 6%) 26/36( 72%)
C: LC33 - LC48 16/16(100%) 3/ 8( 37%) 0/16( 0%) 16/36( 44%)
D: LC49 - LC64 16/16(100%) 3/ 8( 37%) 3/16( 18%) 17/36( 47%)
E: LC65 - LC80 16/16(100%) 3/ 8( 37%) 3/16( 18%) 17/36( 47%)
F: LC81 - LC96 16/16(100%) 2/ 8( 25%) 1/16( 6%) 29/36( 80%)
G: LC97 - LC112 14/16( 87%) 1/ 8( 12%) 1/16( 6%) 31/36( 86%)
H: LC113 - LC128 14/16( 87%) 0/ 8( 0%) 4/16( 25%) 32/36( 88%)
Total dedicated input pins used: 2/4 ( 50%)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -