uartisr.c

FAT16 Filesystem on Philips LPC2000 series processors

#include "types.h"
#include "LPC21xx.h"
#include "uart.h"
#include "uartdefs.h"
#include "armVIC.h"

//////////////////////////////////////////////////////////////////
// this code common to both processors, be carefull not to make
// these functions tied to one processors' features!
//////////////////////////////////////////////////////////////////

// queue and buffer variables.
extern uchar	rx0Buffer [];
extern uchar	tx0Buffer [];
extern volatile ushort	tx0RdQue, tx0WrQue, rx0RdQue, rx0WrQue;
extern volatile bool		tx0Running;

extern uchar	rx1Buffer [];
extern uchar	tx1Buffer [];
extern volatile ushort	tx1RdQue, tx1WrQue, rx1RdQue, rx1WrQue;
extern volatile bool		tx1Running;

extern bool Tx5Active, Rx5Active;

void serial0ISR (void)
{// serial port 0 interrupt handler.
volatile uint8_t IIR;
		// loop until all have been processed.
	while (!((IIR = U0IIR) & UIIR_NO_INT)) {
		switch (IIR & UIIR_ID_MASK) {
			case UIIR_CTI_INT:	// Character Timeout Indicator
			case UIIR_RDA_INT:	// Receive Data Available
				do {	// suck the fifo dry.
					rx0Buffer[rx0WrQue] = U0RBR;		// grab one char.
						// can we mark new char, or do we lose it?
					if (((rx0WrQue+1) & RX0MASK) != rx0RdQue) {
							// we can store it.
						rx0WrQue = (rx0WrQue+1) & RX0MASK;
					}
				} while (U0LSR & ULSR_RDR);
				break;
			case UIIR_THRE_INT:	// Transmit Holding Register Empty
					// anything else "to go" (fries with that? ;-) ?
					// assume transmitter is finished.
				tx0Running = False;
				while (U0LSR & ULSR_THRE) {
						// fill the transmit fifo.
					if (tx0RdQue != tx0WrQue) {
						U0THR = tx0Buffer [tx0RdQue];
						tx0RdQue = (tx0RdQue+1) & TX0MASK;
						tx0Running = True;
					} else break;
				}
				break;
			case UIIR_RLS_INT:	// Receive Line Status
				U0LSR;		// read Line Status Reg to clear.
				break;
			default:			// unknowns, try to clear.
				U0LSR; U0RBR;
				break;
		}
	}
	VICVectAddr = 0x00000000;	// clear interrupt from VIC.
}

void serial1ISR (void)
{// serial port 1 interrupt handler.
volatile uint8_t IIR;
		// loop until all have been processed.
	while (!((IIR = U1IIR) & UIIR_NO_INT)) {
		switch (IIR & UIIR_ID_MASK) {
			case UIIR_MS_INT:	// MODEM Status
				U1MSR;	// read MSR to clear
				break;
			case UIIR_CTI_INT:	// Character Timeout Indicator
			case UIIR_RDA_INT:	// Receive Data Available
				do {	// suck the fifo dry.
					rx1Buffer[rx1WrQue] = U1RBR;		// grab one char.
						// can we mark new char, or do we lose it?
					if (((rx1WrQue+1) & RX1MASK) != rx1RdQue) {
							// we can store it.
						rx1WrQue = (rx1WrQue+1) & RX1MASK;
					}
				} while (U1LSR & ULSR_RDR);
				Rx5Active = True;
				break;
			case UIIR_THRE_INT:	// Transmit Holding Register Empty
					// anything else "to go" (fries with that? ;-) ?
				tx1Running = False;
				while (U1LSR & ULSR_THRE) {
						// fill the transmit fifo.
					if (tx1RdQue != tx1WrQue) {
						U1THR = tx1Buffer [tx1RdQue];
						tx1RdQue = (tx1RdQue+1) & TX1MASK;
						tx1Running = True;
						Tx5Active = True;
					} else break;
				}
				break;
			case UIIR_RLS_INT:	// Receive Line Status
				U1LSR;		// read Line Status Reg to clear.
				break;
			default:			// unknowns, try to clear.
				U1LSR; U1RBR;
				U1MSR;
				break;
		}
	}
	VICVectAddr = 0x00000000;	// clear interrupt from VIC.
}