ask1.vhd

来自「关于幅移键控MPSK调制程序」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ask1 is
port(clk    :in std_logic;
     start  :in std_logic;
     x      :in std_logic;
     y      :out std_logic);
end ask1;
architecture behav of ask1 is
signal q :integer range 0 to 3;
signal f :std_logic;
begin 
process(clk)
begin
if clk'event and clk='1' then 
    if start='0' then q<=0;
    elsif q<=1 then f<='1';q<=q+1;
    elsif q=3 then f<='0';q<=0;
    else f<='0';q<=q+1;
    end if;
end if;
end process;
y<=x and f;
end behav;