dco.vhd

2MHz的数据时钟恢复电路

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dco is
  port(clk: in std_logic;
       reset:  in std_logic;
       decr: in std_logic;
       incr: in std_logic;
       clk_2f0: out std_logic;
       clk_f0: out std_logic);
end dco;

architecture arc_dco of dco is
   type state is(s0,s1,s2,s3,add);
   signal c_state,n_state : state;
   
   signal idout : std_logic;
   --signal clk_in1 : std_logic:='0';
   --signal clk_in2 : std_logic:='0';
   --signal clk_in3 : std_logic:='0';
   signal decr_locked : std_logic;
   signal incr_locked : std_logic;
   signal count : std_logic_vector(2 downto 0):="000";
    
   begin
   
   clk_2f0<=count(1);
   clk_f0<=count(2);    
   
   process
   begin
     wait until clk'event and clk='1' ;
       decr_locked<=decr;
       incr_locked<=incr;
   end process;
   
   process
   begin
     wait until clk'event and clk='1';
       if idout='1' then
         count<=count+1;
       end if;
   end process;      
   
   process(reset,clk)
   begin
     if reset='1' then
       c_state<=s0;
     elsif clk'event and clk='1' then
       c_state<=n_state;
     end if;  
   end process;
   
   process(c_state,incr_locked,decr_locked)
   begin
     n_state<=c_state;
     case c_state is
       when s0 =>
         if decr_locked='1' then
           n_state<=add;
         elsif incr_locked='1' then
           n_state<=s2;
         else
           n_state<=s1;
         end if;
       when s1 =>
         if incr_locked='1' then
           n_state<=s3;
         elsif decr_locked='1' then
           n_state<=s1;
         else  
           n_state<=s2;
         end if; 
       when s2 =>
         if incr_locked='1' then
           n_state<=s0;
         elsif decr_locked='1' then
           n_state<=s2;
         else  
           n_state<=s3;
         end if; 
       when s3 =>
         if incr_locked='1' then
           n_state<=s1;
         elsif decr_locked='1' then
           n_state<=s3;
         else  
           n_state<=s0;
         end if;
       when add =>
         n_state<=s1;   
         
     end case;
   end process;
               
   process
   begin
     wait until clk'event and clk='1';
       if c_state=s0 then 
         idout<='1' ;
       elsif c_state=s3 and incr_locked='1' then
         idout<='1';  
       else
         idout<='0';
       end if;
   end process;
                         
end arc_dco;