filter.vhd

来自「2MHz的数据时钟恢复电路」· VHDL 代码 · 共 52 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity filter is
  port (clk: in std_logic;
        reset:  in std_logic;
        slow: in std_logic;
        fast: in std_logic;
        decr: out std_logic;
        incr: out std_logic);
end filter;

architecture arc_filter of filter is
    signal counter: std_logic_vector(3 downto 0);
    
  begin
              
       process
          begin
             wait until clk'event and clk='1' ;                 
                 if reset='1' then
                       counter<="1000";
                 elsif counter="1111" or counter="0000" then
                       counter<="1000";
                 elsif slow='1' then
                       counter<=counter-1;
                 elsif fast='1' then
                       counter<=counter+1;
                 end if;
      end process;
      
      process
          begin
             wait until clk'event and clk='1' ;
                 if reset='1' then
                      incr<='0';
                      decr<='0';
                 elsif counter="1111" then
                      incr<='0';
                       decr<='1';
                 elsif counter="0000" then
                      incr<='1';
                      decr<='0';
                 else
                      incr<='0';
                      decr<='0';
                 end if;
      end process;  
      
 end arc_filter;