baudrategenerator.txt

uart 的波特率发生器设计

library ieee; 
use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;  --baud rate generator
entity clkunit is
  port(
       sysclk : in std_logic;
       enablerx : out std_logic;
       enabletx : out std_logic;
         reset : in std_logic);
end clkunit;
architecture behaviour of clkunit is
    signal clkdiv26 :  std_logic;
    signal tmpenrx :  std_logic;
    signal tmpentx :  std_logic;
begin       --将主频率40MHz除26或是将20 MHz除13
divclk26 : process(sysclk,reset)
   constant cntone : unsigned(4 downto 0):="00001";
   variable cnt26 : unsigned(4 downto 0);
begin 
   if rising_edge(sysclk) then 
    if reset='0' then
     cnt26:="00000";
     clkdiv26<='0';
    else
     cnt26:=cnt26+cntone;
  case cnt26  is
    when"11010"=>
      clkdiv26<='1';
      cnt26:="00000";
    when others =>
      clkdiv26<='0';
  end case;
  end if;
 end if;
end process;   --若除以5则波特率为19200
divclk10 : process(sysclk,reset,clkdiv26)
  constant cntone :unsigned(3 downto 0):="0001";
  variable cnt10 :unsigned(3 downto 0);
begin 
 if rising_edge(sysclk) then 
    if reset='0' then
     cnt10:="0000";
     tmpenrx <='0'; 
    elsif clkdiv26='1' then
     cnt10:=cnt10+cntone;
    end if;
   case cnt10 is 
when"1010"=>   --或是0101=5
      tmpenrx<='1';
      cnt10:="0000";
when others=>cnt10:=cnt10;
   end case;
 end if;
end process;  -- 设置发送的enabletx信号为9.6KHz
 divclk16 : process(sysclk,reset, tmpenrx)
     constant cntone :unsigned(4 downto 0):="00001";
     variable cnt16 :unsigned(4 downto 0);
begin
  if rising_edge(sysclk) then 
     if reset='0' then
      cnt16:="00000";
      tmpentx <='0'; 
    elsif tmpenrx='1' then 
    cnt16:=cnt16+cntone;
    end if; 
  case cnt16 is 
     when"01111"=>
       tmpentx<='1';
       cnt16:=cnt16+cntone;
     when "10001"=>
      tmpentx<='0';
     when others=>
      tmpentx<='0';
   end case;
 end if;
end process;
 enablerx<=tmpenrx; --将tmpenrx转到输出接口enablerx端
 enabletx<=tmpentx; --将tmpentx转到输出接口enabletx端
end behaviour;