msp430x20x3_ta_17.s43
来自「LSD-EZ430-F2013在IAR环境下的汇编语言开发例程」· S43 代码 · 共 47 行
S43
47 行
;*******************************************************************************
; MSP430F20xx Demo - Timer_A, PWM TA1, Up Mode, 32kHz ACLK
;
; Description: This program generates one PWM outputs on P1.2 using
; Timer_A configured for up mode. The value in CCR0, 512-1, defines the PWM
; period and the value in CCR1 the PWM duty cycle. Using 32kHz
; ACLK as TACLK, the timer period is 15.6ms with a 75% duty cycle on P1.2.
; Normal operating mode is LPM3.
; ACLK = TACLK = LFXT1 = 32768Hz, MCLK = default DCO ~800kHz.
; //* External watch crystal on XIN XOUT is required for ACLK *//
;
; MSP430F20xx
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; | P1.2/TA1|--> CCR1 - 75% PWM
;
; M. Buccini / L. Westlund
; Texas Instruments Inc.
; October 2005
; Built with IAR Embedded Workbench Version: 3.40A
;*******************************************************************************
#include "msp430x20x3.h"
;-------------------------------------------------------------------------------
ORG 0F800h ; Program Reset
;-------------------------------------------------------------------------------
RESET mov.w #0280h,SP ; Initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupP1 bis.b #00Ch,&P1DIR ; P1.2 and P1.3 outputs
bis.b #00Ch,&P1SEL ; P1.2 and P1.3 TA1/2 option
SetupC0 mov.w #512-1,&CCR0 ; PWM Period
SetupC1 mov.w #OUTMOD_7,&CCTL1 ; CCR1 reset/set
mov.w #384,&CCR1 ; CCR1 PWM Duty Cycle
SetupTA mov.w #TASSEL_1+MC_1,&TACTL ; ACLK, upmode
;
Mainloop bis.w #LPM3,SR ; Remain in LPM3
nop ; Required only for debugger
;
;-------------------------------------------------------------------------------
; Interrupt Vectors
;-------------------------------------------------------------------------------
ORG 0FFFEh ; MSP430 RESET Vector
DW RESET ;
END
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