_primary.vhd

EMP1270原理图

library verilog;
use verilog.vl_types.all;
entity fsm is
    port(
        reset           : in     vl_logic;
        enable          : out    vl_logic;
        idle            : in     vl_logic;
        data_in         : inout  vl_logic_vector(7 downto 0);
        address_in      : in     vl_logic_vector(7 downto 0);
        read            : in     vl_logic;
        write           : in     vl_logic;
        scl             : inout  vl_logic;
        busy_bus        : out    vl_logic;
        irq             : out    vl_logic;
        ctrl_w_out      : out    vl_logic;
        start_detected  : in     vl_logic;
        stop_detected   : in     vl_logic;
        start           : out    vl_logic;
        stop            : out    vl_logic;
        ack_slave       : in     vl_logic;
        ack             : out    vl_logic;
        load            : out    vl_logic;
        arbi_lost       : in     vl_logic;
        data_piso_in    : in     vl_logic_vector(7 downto 0);
        nack_slave      : in     vl_logic;
        data_sent_rx    : in     vl_logic;
        data_piso_pec_out: out    vl_logic_vector(7 downto 0);
        rx_pec          : out    vl_logic;
        pec_rx          : in     vl_logic;
        data_pec_in     : in     vl_logic_vector(7 downto 0);
        piso_enable     : out    vl_logic;
        pec_enable      : out    vl_logic;
        count_piso      : in     vl_logic_vector(3 downto 0);
        ena_arbi        : out    vl_logic;
        clk             : in     vl_logic;
        status_reg_4    : out    vl_logic;
        status_reg_3    : out    vl_logic;
        address_reg_0   : out    vl_logic
    );
end fsm;