_primary.vhd

EMP1270原理图

library verilog;
use verilog.vl_types.all;
entity bus_idle_detect is
    port(
        chipselect      : in     vl_logic;
        reset_ext       : in     vl_logic;
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        scl             : inout  vl_logic;
        sd              : in     vl_logic;
        start_detected  : out    vl_logic;
        stop_detected   : out    vl_logic;
        idle            : out    vl_logic;
        enable          : in     vl_logic;
        reset_int       : out    vl_logic
    );
end bus_idle_detect;