_primary.vhd

EMP1270原理图

library verilog;
use verilog.vl_types.all;
entity pec is
    generic(
        crc             : integer := 7
    );
    port(
        reset           : in     vl_logic;
        clk             : in     vl_logic;
        ip_data         : in     vl_logic_vector(7 downto 0);
        op_data         : out    vl_logic_vector(7 downto 0);
        load            : in     vl_logic;
        enable          : in     vl_logic
    );
end pec;