_primary.vhd

EMP1270原理图

library verilog;
use verilog.vl_types.all;
entity output_stage is
    port(
        arbt_failed     : in     vl_logic;
        m_s             : in     vl_logic;
        r_w             : in     vl_logic;
        temp_7          : out    vl_logic;
        ack             : in     vl_logic;
        pec_rcvd        : out    vl_logic;
        rcv_pec         : in     vl_logic;
        enable          : in     vl_logic;
        reset           : in     vl_logic;
        ctrl_w          : in     vl_logic;
        int_clk         : in     vl_logic;
        sda             : inout  vl_logic;
        data_in_b       : in     vl_logic_vector(7 downto 0);
        data_out_b      : out    vl_logic_vector(7 downto 0);
        start_bit       : in     vl_logic;
        stop_bit        : in     vl_logic;
        load_piso       : in     vl_logic;
        data_sent       : out    vl_logic;
        ack_slave       : out    vl_logic;
        nack_slave      : out    vl_logic;
        rd_wrbar_n      : out    vl_logic;
        shift           : out    vl_logic_vector(3 downto 0)
    );
end output_stage;