_primary.vhd

EMP1270原理图

library verilog;
use verilog.vl_types.all;
entity mod_crc is
    port(
        reset           : in     vl_logic;
        enable          : in     vl_logic;
        ack             : in     vl_logic;
        data_in         : in     vl_logic_vector(7 downto 0);
        load_s          : in     vl_logic;
        clk             : in     vl_logic;
        data_out        : out    vl_logic_vector(7 downto 0)
    );
end mod_crc;