fangzhen.mdl

LPC编码与解码

	  Name			  "ResidO"
	  Position		  [240, 253, 270, 267]
	  Port			  "2"
	}
	Line {
	  SrcBlock		  "6-bit\nQuantizer"
	  SrcPort		  1
	  DstBlock		  "ResidO"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "ResidI"
	  SrcPort		  1
	  DstBlock		  "6-bit\nQuantizer"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "5-bit\nQuantizer"
	  SrcPort		  1
	  DstBlock		  "LPCO"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "LPCI"
	  SrcPort		  1
	  DstBlock		  "5-bit\nQuantizer"
	  DstPort		  1
	}
	Annotation {
	  Name			  "Inverse Sine LPC parameters fall in\nthe ra"
"nge [-pi/2, pi/2].  Quantizing\ninto steps of 0.1 yields approx. 32 steps\n(5"
" bits of precision)."
	  Position		  [167, 174]
	}
	Annotation {
	  Name			  "Residual is generally in the range [-1,+1]."
"\nQuantizing into steps of .03125 yields\napprox. 64 steps (6 bits of precisi"
"on)."
	  Position		  [167, 329]
	}
	Annotation {
	  Name			  "Simulates an 11-bit quantized bit stream\nf"
"or efficient transmission of coder parameters"
	  Position		  [166, 27]
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "LPC\nAnalysis"
      Ports		      [1, 2]
      Position		      [260, 92, 340, 163]
      TreatAsAtomicUnit	      off
      System {
	Name			"LPC\nAnalysis"
	Location		[43, 323, 988, 556]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In"
	  Position		  [25, 48, 50, 72]
	}
	Block {
	  BlockType		  Reference
	  Name			  "Autocorrelation"
	  Ports			  [1, 1]
	  Position		  [325, 35, 375, 85]
	  SourceBlock		  "dspstat3/Autocorrelation"
	  SourceType		  "Autocorrelation"
	  AllPositiveLags	  "off"
	  maxlag		  "10"
	  bias			  "Biased"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Levinson-\nDurbin"
	  Ports			  [1, 1]
	  Position		  [395, 36, 455, 84]
	  SourceBlock		  "dspsolvers/Levinson-Durbin"
	  SourceType		  "Levinson Solver"
	  coeffOutFcn		  "K"
	  outP			  "off"
	  zeroInpHandling	  "on"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Overlap\nAnalysis\nWindows"
	  Ports			  [1, 1]
	  Position		  [185, 33, 235, 87]
	  SourceBlock		  "dspbuff3/Buffer"
	  SourceType		  "Buffer"
	  N			  "160"
	  V			  "80"
	  ic			  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Pre-\nEmphasis"
	  Ports			  [1, 1]
	  Position		  [80, 38, 150, 82]
	  SourceBlock		  "dsparch3/Direct-Form II\nTranspose Filter"
	  SourceType		  "Direct-Form II Transpose Filter"
	  num			  "[1 -.95]"
	  den			  "1"
	  ic			  "0"
	}
	Block {
	  BlockType		  Trigonometry
	  Name			  "RC to InvSine"
	  Ports			  [1, 1]
	  Position		  [625, 95, 655, 125]
	  Operator		  "asin"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Time-Varying\nAnalysis Filter"
	  Ports			  [2, 1]
	  Position		  [495, 24, 575, 71]
	  SourceBlock		  "dsparch3/Time-Varying\nLattice Filter"
	  SourceType		  "Time-Varying Lattice Filter"
	  ARMA			  "All-Zero (MA)"
	  ic			  "0"
	  FiltPerFrame		  "One Filter Per Frame Time"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Window"
	  Ports			  [1, 1]
	  Position		  [255, 34, 305, 86]
	  SourceBlock		  "dspsigops/Window\nFunction"
	  SourceType		  "Window Function"
	  winmode		  "Apply window to input"
	  wintype		  "Hamming"
	  N			  "64"
	  Rs			  "50"
	  beta			  "10"
	  winsamp		  "Symmetric"
	  UserWindow		  "hamming"
	  OptParams		  "off"
	  UserParams		  "{1.0}"
	  datatype		  "Double"
	}
	Block {
	  BlockType		  Outport
	  Name			  "LPC"
	  Position		  [685, 99, 710, 121]
	}
	Block {
	  BlockType		  Outport
	  Name			  "Resid"
	  Position		  [645, 38, 670, 62]
	  Port			  "2"
	}
	Line {
	  SrcBlock		  "Pre-\nEmphasis"
	  SrcPort		  1
	  Points		  [0, 0; 15, 0]
	  Branch {
	    Points		    [0, -45; 310, 0]
	    DstBlock		    "Time-Varying\nAnalysis Filter"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Overlap\nAnalysis\nWindows"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Overlap\nAnalysis\nWindows"
	  SrcPort		  1
	  DstBlock		  "Window"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Autocorrelation"
	  SrcPort		  1
	  DstBlock		  "Levinson-\nDurbin"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Window"
	  SrcPort		  1
	  DstBlock		  "Autocorrelation"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Levinson-\nDurbin"
	  SrcPort		  1
	  Points		  [0, 0; 5, 0]
	  Branch {
	    DstBlock		    "Time-Varying\nAnalysis Filter"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 50]
	    DstBlock		    "RC to InvSine"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "RC to InvSine"
	  SrcPort		  1
	  DstBlock		  "LPC"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In"
	  SrcPort		  1
	  DstBlock		  "Pre-\nEmphasis"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Time-Varying\nAnalysis Filter"
	  SrcPort		  1
	  DstBlock		  "Resid"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "LPC\nSynthesis"
      Ports		      [2, 1]
      Position		      [485, 93, 565, 162]
      TreatAsAtomicUnit	      off
      System {
	Name			"LPC\nSynthesis"
	Location		[80, 299, 652, 457]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "LPC"
	  Position		  [70, 73, 95, 97]
	}
	Block {
	  BlockType		  Inport
	  Name			  "Resid"
	  Position		  [70, 28, 95, 52]
	  Port			  "2"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Direct-Form II\nDe-emphasis Filter"
	  Ports			  [1, 1]
	  Position		  [300, 28, 370, 72]
	  SourceBlock		  "dsparch3/Direct-Form II\nTranspose Filter"
	  SourceType		  "Direct-Form II Transpose Filter"
	  num			  "1"
	  den			  "[1 -.95]"
	  ic			  "0"
	}
	Block {
	  BlockType		  Trigonometry
	  Name			  "InvSine\nto RC"
	  Ports			  [1, 1]
	  Position		  [120, 70, 150, 100]
	}
	Block {
	  BlockType		  Reference
	  Name			  "Time-Varying\nSynthesis Filter"
	  Ports			  [2, 1]
	  Position		  [180, 28, 270, 72]
	  SourceBlock		  "dsparch3/Time-Varying\nLattice Filter"
	  SourceType		  "Time-Varying Lattice Filter"
	  ARMA			  "All-Pole (AR)"
	  ic			  "0"
	  FiltPerFrame		  "One Filter Per Frame Time"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out"
	  Position		  [425, 38, 450, 62]
	}
	Line {
	  SrcBlock		  "Time-Varying\nSynthesis Filter"
	  SrcPort		  1
	  DstBlock		  "Direct-Form II\nDe-emphasis Filter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Resid"
	  SrcPort		  1
	  DstBlock		  "Time-Varying\nSynthesis Filter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "LPC"
	  SrcPort		  1
	  DstBlock		  "InvSine\nto RC"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "InvSine\nto RC"
	  SrcPort		  1
	  Points		  [10, 0]
	  DstBlock		  "Time-Varying\nSynthesis Filter"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Direct-Form II\nDe-emphasis Filter"
	  SrcPort		  1
	  DstBlock		  "Out"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "To Wave\nDevice"
      Ports		      [1]
      Position		      [620, 104, 675, 156]
      SourceBlock	      "dspwin32/To Wave\nDevice"
      SourceType	      "To Wave Device"
      bufDuration	      "1"
      initDelay		      "0.1"
      useDefaultDevice	      on
      userDeviceID	      "Realtek HD Audio output"
      enable24Bit	      off
    }
    Line {
      SrcBlock		      "LPC\nAnalysis"
      SrcPort		      1
      DstBlock		      "Bit Stream\nQuantization"
      DstPort		      1
    }
    Line {
      SrcBlock		      "LPC\nAnalysis"
      SrcPort		      2
      DstBlock		      "Bit Stream\nQuantization"
      DstPort		      2
    }
    Line {
      SrcBlock		      "8 kHz\nSignal\n\"MATLAB\""
      SrcPort		      1
      DstBlock		      "LPC\nAnalysis"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Bit Stream\nQuantization"
      SrcPort		      2
      DstBlock		      "LPC\nSynthesis"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Bit Stream\nQuantization"
      SrcPort		      1
      DstBlock		      "LPC\nSynthesis"
      DstPort		      1
    }
    Line {
      SrcBlock		      "LPC\nSynthesis"
      SrcPort		      1
      DstBlock		      "To Wave\nDevice"
      DstPort		      1
    }
  }
}