xt.mdl

实现lpc脉冲编码仿真

Model {
  Name			  "xt"
  Version		  5.0
  SaveDefaultBlockParams  on
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ExecutionOrder	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Wed Apr 28 10:40:09 2004"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "founder"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Wed Apr 28 10:53:32 2004"
  ModelVersionFormat	  "1.%<AutoIncrement:1>"
  ConfigurationManager	  "None"
  SimParamPage		  "Solver"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  RTWExpressionDepthLimit 5
  SimulationMode	  "normal"
  Solver		  "ode45"
  SolverMode		  "Auto"
  StartTime		  "0.0"
  StopTime		  "10.0"
  MaxOrder		  5
  MaxStep		  "auto"
  MinStep		  "auto"
  MaxNumMinSteps	  "-1"
  InitialStep		  "auto"
  FixedStep		  "auto"
  RelTol		  "1e-3"
  AbsTol		  "auto"
  OutputOption		  "RefineOutputTimes"
  OutputTimes		  "[]"
  Refine		  "1"
  LoadExternalInput	  off
  ExternalInput		  "[t, u]"
  LoadInitialState	  off
  InitialState		  "xInitial"
  SaveTime		  on
  TimeSaveName		  "tout"
  SaveState		  off
  StateSaveName		  "xout"
  SaveOutput		  on
  OutputSaveName	  "yout"
  SaveFinalState	  off
  FinalStateName	  "xFinal"
  SaveFormat		  "Array"
  Decimation		  "1"
  LimitDataPoints	  on
  MaxDataPoints		  "1000"
  SignalLoggingName	  "sigsOut"
  ConsistencyChecking	  "none"
  ArrayBoundsChecking	  "none"
  AlgebraicLoopMsg	  "warning"
  BlockPriorityViolationMsg "warning"
  MinStepSizeMsg	  "warning"
  InheritedTsInSrcMsg	  "warning"
  DiscreteInheritContinuousMsg "warning"
  MultiTaskRateTransMsg	  "error"
  SingleTaskRateTransMsg  "none"
  CheckForMatrixSingularity "none"
  IntegerOverflowMsg	  "warning"
  Int32ToFloatConvMsg	  "warning"
  ParameterDowncastMsg	  "error"
  ParameterOverflowMsg	  "error"
  ParameterPrecisionLossMsg "warning"
  UnderSpecifiedDataTypeMsg "none"
  UnnecessaryDatatypeConvMsg "none"
  VectorMatrixConversionMsg "none"
  InvalidFcnCallConnMsg	  "error"
  SignalLabelMismatchMsg  "none"
  UnconnectedInputMsg	  "warning"
  UnconnectedOutputMsg	  "warning"
  UnconnectedLineMsg	  "warning"
  SfunCompatibilityCheckMsg "none"
  RTWInlineParameters	  off
  BlockReductionOpt	  on
  BooleanDataType	  on
  ConditionallyExecuteInputs on
  ParameterPooling	  on
  OptimizeBlockIOStorage  on
  ZeroCross		  on
  AssertionControl	  "UseLocalSettings"
  ProdHWDeviceType	  "Microprocessor"
  ProdHWWordLengths	  "8,16,32,32"
  RTWSystemTargetFile	  "grt.tlc"
  RTWTemplateMakefile	  "grt_default_tmf"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  RTWRetainRTWFile	  off
  TLCProfiler		  off
  TLCDebug		  off
  TLCCoverage		  off
  TLCAssertion		  off
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Inport
      Port		      "1"
      PortDimensions	      "-1"
      SampleTime	      "-1"
      ShowAdditionalParam     off
      LatchInput	      off
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Logic
      Operator		      "AND"
      Inputs		      "2"
      ShowAdditionalParam     off
      AllPortsSameDT	      on
      OutDataTypeMode	      "Logical (see Advanced Sim. Parameters)"
      LogicDataType	      "uint(8)"
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      PortCounts	      "[]"
      SFunctionModules	      "''"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      RTWSystemCode	      "Auto"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "xt"
    Location		    [480, 93, 1060, 386]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem"
      Ports		      [2, 2]
      Position		      [240, 89, 340, 131]
      FontSize		      10
      TreatAsAtomicUnit	      off
      System {
	Name			"Subsystem"
	Location		[424, 327, 922, 627]
	Open			on
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [105, 103, 135, 117]
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [105, 193, 135, 207]
	  Port			  "2"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Dot Product"
	  Ports			  [2, 1]
	  Position		  [225, 101, 255, 134]
	  SourceBlock		  "simulink/Math\nOperations/Dot Product"
	  SourceType		  "Dot Product"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Dot Product1"
	  Ports			  [2, 1]
	  Position		  [225, 161, 255, 194]
	  SourceBlock		  "simulink/Math\nOperations/Dot Product"
	  SourceType		  "Dot Product"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [1, 1]
	  Position		  [170, 184, 200, 216]
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [325, 113, 355, 127]
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out2"
	  Position		  [325, 173, 355, 187]
	  Port			  "2"
	}
	Line {
	  Labels		  [1, 0]
	  SrcBlock		  "In2"
	  SrcPort		  1
	  Points		  [30, 0]
	  Branch {
	    DstBlock		    "Logical\nOperator"
	    DstPort		    1
	  }
	  Branch {
	    Labels		    [2, 0]
	    Points		    [-25, 0; 0, -75]
	    DstBlock		    "Dot Product"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Dot Product"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 60]
	    DstBlock		    "Dot Product1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Dot Product"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  Points		  [5, 0]
	  DstBlock		  "Dot Product1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Dot Product1"
	  SrcPort		  1
	  DstBlock		  "Out2"
	  DstPort		  1
	}
	Annotation {
	  Position		  [205, 198]
	}
      }
    }
  }
}