780547.h

ucos在NEC平台下的移植

//-----------------------------------------------------------------------------
//
//	file:			780547.h
//	description:	demonstration program, definition of registers
//	Version:		1.0
//
//-------------------------------------------------------------------------------
#ifndef	__78F0547_H__
#define	__78F0547_H__

/////////////////////////////////////////////////////////////////////
//	CPUS
#define	MAIN_CLOCK		(16.0000f)		// Main Clock MHz (for debug)
#define	SUB_CLOCK		(32.768f)		// Sub Clock  32.768KHz

/////////////////////////////////////////////////////////////////////
//	I/O port
//-----------------------------------------------
//	P0

//	unused port should be set as OUTPUT.
//		
#define	P0_DIR			0b01101011
#define	P0_PULLUP		0b01101011
/* P0
    |------+------+------+------|------+------+------+------|
    | NONE | SFD  |SW1_8 | SCLK | SO   | SI   |SW1_7 |SW1_6 |
    |------+------+------+------|------+------+------+------|
PM		0		1		1	0		1		0		1	1
(in=1, out=0)
PD		0		1		0	1		0		0		0	0
PU		0		1		1	0		1		0		1	1
(pup=1)
*/
#define	SW1_8			(P0.5)
#define	SW1_7			(P0.1)
#define	SW1_6			(P0.0)

//-----------------------------------------------
//	P1

#define	P1_DIR			0b00010000

/* P1
    |------+------+------+------|------+------+------+------|
    | P17  | P16  | P15  | TXD  | RXD  | P12  | P11  |P10   |
    |------+------+------+------|------+------+------+------|
PM		0		0		0	1		0		0		0	0
(in=1, out=0)
PD		0		0		0	0		1		0		0	0
PU		0		0		0	0		0		0		0	0
(pup=1)
*/

//-----------------------------------------------
//	P2

#define	P2_DIR			0b11111111

//		P20/ANI0	Power Monitor
//		P24-P26					(ext. I/O)
//		P21-P27		not use		INPUT only


//-----------------------------------------------
//	P3

#define	P3_DIR			0b11111111
#define	P3_PULLUP		0b00000000

/* P3
    |------+------+------+------|------+------+------+------|
    | NONE | NONE | NONE | NONE | P33  | P32  | P31  |FIFOP |
    |------+------+------+------|------+------+------+------|
PM		1		1		1	1		1		1		1	1
(in=1, out=0)
PD		0		0		0	0		0		0		0	0
PU		0		0		0	0		0		0		0	0
(pup=1)
*/

//-----------------------------------------------
//	P4

#define	P4_DIR			0b00000000

/* P4
    |------+------+------+------|------+------+------+------|
    | NC   | NC   | NC   | NC   | CSn  | LED4 | LED3 |LED2  |
    |------+------+------+------|------+------+------+------|
PM		0		0		0	0		0		0		0	0
(in=1, out=0)
PD		0		0		0	0		1		0		0	0
PU		0		0		0	0		0		0		0	0
(pup=1)
*/

#define	LED2			(P4.0)
#define	LED3			(P4.1)
#define	LED4			(P4.2)

#define	LED_OFF(a)		((a) = TRUE)
#define	LED_ON(a)		((a) = FALSE)

//-----------------------------------------------
//	P5

#define	P5_DIR			0b00001100
#define P5_PULLUP		0b00001000

/* P5
    |------+------+------+------|------+------+------+------|
    | NC   | NC   | NC   | NC   | CCA  | FIFO | RESn |VREG  |
    |------+------+------+------|------+------+------+------|
PM		0		0		0	0		1		1		0	0
(in=1, out=0)
PD		0		0		0	0		0		0		0	1
PU		0		0		0	0		1		0		0	0
(pup=1)
*/

//-----------------------------------------------
//	P6

#define	P6_DIR			0b00000000
#define	P6_PULLUP		0b00000000

/* P6
    |------+------+------+------|------+------+------+------|
    | NC   | NC   | NC   | NC   | NC   |P62   |P61   |P60   |
    |------+------+------+------|------+------+------+------|
PM		0		0		0	0		0		0		0	0
(in=1, out=0)
PD		0		0		0	0		0		0		0	0
PU		0		0		0	0		0		0		0	0
(pup=1)
*/

//-----------------------------------------------
//	P7

#define	P7_DIR			0b11111111
#define	P7_PUP			0b01111111
#define	SW_DETECT		0b01111111

#define	TACT_SW4		((P7.1)==0)
#define	TACT_SW3		((P7.0)==0)

/* P7
    |------+------+------+------|------+------+------+------|
    |FLMD0 |SW1伀 |SW1仺 |SW1仼 |SW1丒 |SW1仾 |SW4   |SW3   |
    |------+------+------+------|------+------+------+------|
PM		1		1		1	1		1		1		1	1
(in=1, out=0)
PD		0		0		0	0		0		0		0	0
PU		0		1		1	1		1		1		1	1
(pup=1)
*/

//-----------------------------------------------
//	P14

#define	P14_DIR			0b00000000
#define	P14_PULLUP		0b00000000

/* P14
    |------+------+------+------|------+------+------+------|
    |NONE  |NONE  |NC    |NC    |NC    |NC    |P141  |P140  |
    |------+------+------+------|------+------+------+------|
PM		0		0		0	0		0		0		0	0
(in=1, out=0)
PD		0		0		0	0		0		0		0	0
PU		0		0		0	0		0		0		0	0
(pup=1)
*/

/////////////////////////////////////////////////////////////////////
//	I/O level

/////////////////////////////////////////////////////////////////////
//	Serial port

	// Serial interface status register
#define	ASIS_PE				0x04
#define	ASIS_FE				0x02
#define	ASIS_OVE			0x01

	// Serial interface tx status register
#define	ASIF_TXBF			0x02
#define	ASIF_TXSF			0x01

	// (UART_MODE)Serial interface mode register
#define	ASIM_POWER			0x80
#define	ASIM_TXE			0x40
#define	ASIM_RXE			0x20
#define	ASIM_PS0			0x10
#define	ASIM_PS1			0x08
#define	ASIM_CL				0x04
#define	ASIM_SL				0x02
#define	ASIM_ISRM			0x01

//-----------------------------------------------
//	Serial port
#if	USE_UART0		/////////////////////////////////////////////////

#define	UART_RX				RXB0
#define	UART_TX				TXS0
#define	UART_RX_STATUS		ASIS0
#define	UART_BRGC			BRGC0
#define	UART_MODE			ASIM0

#define	UART_TX_INT_MASK	DUALMK0			// INTST0 = CSI10
#define	UART_RX_INT_MASK	SRMK0			// INTSR0

		// pulse	(10MHz/16MHz)
#define	CKSEL_9600			3
#define	CKSEL_19200			3
#define	CKSEL_38400			2

		// Base Clock	(16MHz)	-- BRGC2(MDL27-20)
#define	BRGC_9600			26
#define	BRGC_19200			13
#define	BRGC_38400			26

#else	// UART6	////////////////////////////////////////////////

#define	UART_RX				RXB6
#define	UART_TX				TXB6
#define	UART_RX_STATUS		ASIS6
#define	UART_TX_STATUS		ASIF6
#define	UART_BRGC			BRGC6
#define	UART_MODE			ASIM6
#define	UART_CLOCK			CKSR6

#define	UART_TX_INT_MASK	STMK6			// INTST6
#define	UART_RX_INT_MASK	SRMK6			// INTSR6
#define	UART_ERR_INT_MASK	SREMK6

		// pulse	(10MHz/16MHz)
#define	CKSEL_9600			2
#define	CKSEL_19200			1
#define	CKSEL_38400			0

		// Base Clock	(16MHz)	-- BRGC2(MDL27-20)
#define	BRGC_9600			208
#define	BRGC_19200			208
#define	BRGC_38400			208

#endif

#define	DISABLE_RECEIVE()	{UART_MODE=(UART_MODE & ~ASIM_RXE);}
#define	ENABLE_RECEIVE()	{UART_MODE=(UART_MODE | ASIM_RXE);}

/////////////////////////////////////////////////////////////////////
//	Interrupt

//	Serial (0 or 6)
#define	SET_UART_MASK()		{ UART_TX_INT_MASK=TRUE; UART_RX_INT_MASK=TRUE; }
#define	CLEAR_UART_MASK()	{ UART_TX_INT_MASK=FALSE; UART_RX_INT_MASK=FALSE; }

//	Key
#define	SET_KEY_MASK()		{ KRMK = TRUE; }
#define	CLEAR_KEY_MASK()	{ KRMK = FALSE; }

//	FIFOP (CC2420)
#define	SET_FIFOP_MASK()	{ PMK1 = TRUE; }
#define	CLEAR_FIFOP_MASK()	{ PMK1 = FALSE; }

#endif	// __78F0547_H__