sam9261.s

reference about 9261,refernce tc timer!

;//                   <3=> PLL B Clock
;//     <o8.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 2 (PMC_PCK2)
;//     <o9.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o9.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 3 (PMC_PCK3)
;//     <o10.0..1>  CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o10.2..4>  PRES: Programmable Clock Prescaler
;//                   <0=> None         <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;// </e>
PMC_SETUP       EQU     1
PMC_SCER_Val    EQU     0x00000001
PMC_PCER_Val    EQU     0x00000018
CKGR_MOR_Val    EQU     0x0000FF01
CKGR_PLLAR_Val  EQU     0x20483F0E
CKGR_PLLBR_Val  EQU     0x00000000
PMC_MCKR_Val    EQU     0x00000002
PMC_PCK0_Val    EQU     0x00000000
PMC_PCK1_Val    EQU     0x00000000
PMC_PCK2_Val    EQU     0x00000000
PMC_PCK3_Val    EQU     0x00000000


;----------------------- Watchdog (WDT) Definitions ----------------------------

; Watchdog
WDT_BASE        EQU     0xFFFFFD40      ; WDT                     Base Address
WDT_MR_OFS      EQU     0x04            ; Watchdog Timer Mode Reg Address Offset

;// <e0.15> Watchdog Disable
;// </e>
WDT_Val         EQU     0x00008000


;----------------------- Cache Definitions -------------------------------------

; Cache

; Constants
ICACHE_ENABLE   EQU     (1<<12)         ; Instruction Cache Enable Bit

;// <e> Instruction Cache Enable
;// </e>
ICACHE_SETUP    EQU     1


;----------------------- Tightly-Coupled Memory (TCM) Definitions --------------

; Tightly-Coupled Memory

; Constants
TCM_ENABLE      EQU     (1<<0)          ; Instruction TCM Enable Bit

;// <e> Tightly-Coupled Memory Enable
;//
TCM_SETUP       EQU     0

;//   <h> Instruction TCM Configuration
;//     <o0.0..3>  Size of Instruction TCM enabled memory block
;//                     <0=> 0K Bytes
;//                     <5=> 16K Bytes
;//                     <6=> 32K Bytes
;//                     <7=> 64K Bytes
;//
;//     <o1.0..19> Address of Instruction TCM (in 4K Bytes regions) <0x00000-0xFFFFF>
;//                     <i> Example: For physical address 0x00100000 the Address should
;//                     <i> be set to 0x00100
;//
;//   </h>
;//
ITCM_SIZE_Val   EQU     0
ITCM_ADDR_Val   EQU     0x00100

;//   <h> Data TCM Configuration
;//     <o0.0..3>  Size of Data TCM enabled memory block
;//                     <0=> 0K Bytes
;//                     <5=> 16K Bytes
;//                     <6=> 32K Bytes
;//                     <7=> 64K Bytes
;//
;//     <o1.0..19> Address of Data TCM (in 4K Bytes regions) <0x00000-0xFFFFF>
;//                     <i> Example: For physical address 0x00200000 the Address should
;//                     <i> be set to 0x00200
;//
;//   </h>
;//
DTCM_SIZE_Val   EQU     0
DTCM_ADDR_Val   EQU     0x00200

;// </e>


;----------------------- CODE --------------------------------------------------

                PRESERVE8
                

; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.

                AREA    RESET, CODE, READONLY
                ARM

                IF      :DEF:SIZE_INFO
                IMPORT  ||Image$$ER_ROM1$$RO$$Length||
                IMPORT  ||Image$$RW_RAM1$$RW$$Length||
                ENDIF

; Exception Vectors
;  Mapped to Address 0.
;  Absolute addressing mode must be used.
;  Dummy Handlers are implemented as infinite loops which can be modified.

Vectors         LDR     PC,Reset_Addr         
                LDR     PC,Undef_Addr
                LDR     PC,SWI_Addr
                LDR     PC,PAbt_Addr
                LDR     PC,DAbt_Addr
                ; Reserved vector is used as size information for 2-nd level 
                ; bootloader to use when copying program code to External SDRAM
                IF      :DEF:SIZE_INFO
                  DCD   ||Image$$ER_ROM1$$RO$$Length||+\
                        ||Image$$RW_RAM1$$RW$$Length||
                ELSE
                  NOP
                ENDIF
                LDR     PC,[PC,#-0xF20] ; Vector From AIC_IVR
                LDR     PC,[PC,#-0xF20] ; Vector From AIC_FVR

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
                DCD     0               ; Reserved Address
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler

Undef_Handler   B       Undef_Handler
SWI_Handler     B       SWI_Handler
PAbt_Handler    B       PAbt_Handler
DAbt_Handler    B       DAbt_Handler
IRQ_Handler     B       IRQ_Handler
FIQ_Handler     B       FIQ_Handler


; Reset Handler

                EXPORT  Reset_Handler
Reset_Handler   


; Setup Static Memory Controller (SMC) -----------------------------------------

                ; Setup Static Memory Controller if enabled
                IF      SMC_SETUP != 0
                LDR     R0, =SMC_BASE

                ; Macro for setting the Static Memory Controller
                MACRO
$label          SMC_Cod $cs

$label          LDR     R1, =SMC_SETUP$cs._Val
                STR     R1, [R0, #SMC_SETUP$cs._OFS]
                LDR     R1, =SMC_PULSE$cs._Val
                STR     R1, [R0, #SMC_PULSE$cs._OFS]
                LDR     R1, =SMC_CYCLE$cs._Val
                STR     R1, [R0, #SMC_CYCLE$cs._OFS]
                LDR     R1, =SMC_MODE$cs._Val
                STR     R1, [R0, #SMC_MODE$cs._OFS]
                MEND

                IF      SMC_CS0_SETUP != 0  ; Setup SMC for CS0 if required
SMC_0           SMC_Cod 0
                ENDIF
                IF      SMC_CS1_SETUP != 0  ; Setup SMC for CS1 if required
SMC_1           SMC_Cod 1
                ENDIF
                IF      SMC_CS2_SETUP != 0  ; Setup SMC for CS2 if required
SMC_2           SMC_Cod 2
                ENDIF
                IF      SMC_CS3_SETUP != 0  ; Setup SMC for CS3 if required
SMC_3           SMC_Cod 3
                ENDIF
                IF      SMC_CS4_SETUP != 0  ; Setup SMC for CS4 if required
SMC_4           SMC_Cod 4
                ENDIF
                IF      SMC_CS5_SETUP != 0  ; Setup SMC for CS5 if required
SMC_5           SMC_Cod 5
                ENDIF
                IF      SMC_CS6_SETUP != 0  ; Setup SMC for CS6 if required
SMC_6           SMC_Cod 6
                ENDIF
                IF      SMC_CS7_SETUP != 0  ; Setup SMC for CS7 if required
SMC_7           SMC_Cod 7
                ENDIF

                ENDIF   ; of IF      SMC_SETUP != 0


; Setup Bus Matrix (MATRIX) ----------------------------------------------------

                IF      MATRIX_SETUP != 0
                LDR     R0, =MATRIX_BASE

                LDR     R1, =MATRIX_SCFG0_Val
                STR     R1, [R0, #MATRIX_SCFG0_OFS]

                LDR     R1, =MATRIX_SCFG1_Val
                STR     R1, [R0, #MATRIX_SCFG1_OFS]

                LDR     R1, =MATRIX_SCFG2_Val
                STR     R1, [R0, #MATRIX_SCFG2_OFS]

                LDR     R1, =MATRIX_SCFG3_Val
                STR     R1, [R0, #MATRIX_SCFG3_OFS]

                LDR     R1, =MATRIX_SCFG4_Val
                STR     R1, [R0, #MATRIX_SCFG4_OFS]
                ENDIF   ; of IF      MATRIX_SETUP != 0

; Setup External Bus Interface (EBI) -------------------------------------------

                IF      EBI_SETUP != 0
                LDR     R0, =MATRIX_BASE
                LDR     R1, =EBI_CSA_Val
                STR     R1, [R0, #EBI_CSA_OFS]
                ENDIF   ; of IF      EBI_SETUP != 0


; Setup SDRAM Controller (SDRAMC) ----------------------------------------------

                ; Setup SDRAM Controller if enabled
                IF      :DEF:NO_SDRAM_INIT
                ELSE
                IF      SDRAMC_SETUP != 0

                ; Setup Parallel Input/Output C Regist