sam9261.s

reference about 9261,refernce tc timer!

;//       <o3.16..24> NRD_CYCLE: Total Read Cycle Length <0-511>
;//                     <i> Read cycle length = (NRD_CYCLE[8..7]*256+NRD_CYCLE[6..0]) clock cycle
;//     </h>
;//
;//     <h> Chip Select 7 Mode Register (SMC_MODE7)
;//       <o4.0>      READ_MODE:
;//                     <0=> The read operation is controlled by the NCS signal
;//                     <1=> The read operation is controlled by the NRD signal
;//       <o4.1>      WRITE_MODE:
;//                     <0=> The write operation is controlled by the NCS signal
;//                     <1=> The write operation is controlled by the NWE signal
;//       <o4.4..5>   EXNW_MODE: NWAIT Mode
;//                     <0=> Disabled
;//                     <2=> Frozen Mode
;//                     <3=> Ready Mode
;//       <o4.8>      BAT: Byte Access Type
;//                     <0=> 0
;//                     <1=> 1
;//                     <i>  0: - Write operation is controlled using: NCS, NWE, NBS0, NBS1, NBS2, NBS3
;//                     <i>     - Read  operation is controlled using: NCS, NRD, NBS0, NBS1, NBS2, NBS3
;//                     <i>  1: - Write operation is controlled using: NCS, NWR0, NWR1, NWR2, NWR3        
;//                     <i>     - Read  operation is controlled using: NCS, NRD
;//       <o4.12..13> DBW: Data Bus Width
;//                     <0=> 8-bit bus
;//                     <1=> 16-bit bus
;//                     <2=> 32-bit bus
;//       <o4.16..19> TDF_CYCLES: Data Float Time <0-15>
;//       <o4.20>     TDF_MODE: TDF Optimization Enabled
;//       <o4.24>     PMEN: Page Mode Enabled
;//       <o4.28..29> PS: Page Size
;//                     <0=> 4-byte page
;//                     <1=> 8-byte page
;//                     <2=> 16-byte page
;//                     <3=> 32-byte page
;//     </h>
;//   </e>
SMC_CS7_SETUP   EQU     0x00000000
SMC_SETUP7_Val  EQU     0x00000000
SMC_PULSE7_Val  EQU     0x01010101
SMC_CYCLE7_Val  EQU     0x00010001
SMC_MODE7_Val   EQU     0x10001000

;// </e> Static Memory Controller (SMC)


;----------------------- SDRAM Controller (SDRAMC) Definitions -----------------

; SDRAM Controller (SDRAMC) User Interface
SDRAMC_BASE     EQU     0xFFFFEA00      ; SDRAMC                 Base Address
SDRAMC_MR_OFS   EQU     0x00            ; Mode Register          Address Offsett
SDRAMC_TR_OFS   EQU     0x04            ; Refresh Timer Register Address Offsett
SDRAMC_CR_OFS   EQU     0x08            ; Configuration Register Address Offsett
SDRAMC_HSR_OFS  EQU     0x0C            ; High Speed Register    Address Offsett

; Constants
CMD_NORMAL      EQU     0x00            ; SDRAM Normal Mode
CMD_NOP         EQU     0x01            ; SDRAM NOP Command
CMD_PRCGALL     EQU     0x02            ; SDRAM All Banks Precharge Command
CMD_LMR         EQU     0x03            ; SDRAM Load Mode Register Command
CMD_RFSH        EQU     0x04            ; SDRAM Refresh Command

;// <e> SDRAM Controller (SDRAMC)
SDRAMC_SETUP    EQU     1

;//   <h> Refresh Timer Register (SDRAMC_TR)
;//     <o0.0..11>  COUNT: SDRAMC Refresh Timer Count <0-4095>
;//                   <i> This 12-bit field is loaded into a timer that generates
;//                   <i> the refresh pulse
;//   </h>
SDRAMC_TR_Val   EQU     0x0000011F

;//   <h> Configuration Register (SDRAMC_CR)
;//     <o0.0..1>   NC: Number of Column Bits
;//                   <0=> 8  <1=> 9  <2=> 10 <3=> 11
;//     <o0.2..3>   NR: Number of Row Bits
;//                   <0=> 11 <1=> 12 <2=> 13
;//     <o0.4>      NB: Number of Banks
;//                   <0=> 2  <1=> 4
;//     <o0.5..6>   CAS: CAS Latency
;//                   <1=> 1  <2=> 2  <3=> 3
;//     <o0.7>      DBW: Data Bus Width
;//                   <0=> 32 bits              <1=> 16 bits
;//     <o0.8..11>  TWR: Write Recovery Delay <0-15>
;//                   <i> Defines Write Recovery Time, in cycles
;//     <o0.12..15> TRC: Row Cycle Delay      <0-15>
;//                   <i> Defines delay between Refresh and an Activate 
;//                   <i> Command, in cycles
;//     <o0.16..19> TRP: Row Precharge Delay  <0-15>
;//                   <i> Defines delay between Precharge Command
;//                   <i> and another Command, in cycles
;//     <o0.20..23> TRCD: Row to Column Delay <0-15>
;//                   <i> Defines delay between Activate Command
;//                   <i> and a Read/Write Command, in cycles
;//     <o0.24..27> TRAS: Active to Precharge Delay <0-15>
;//                   <i> Defines delay between Activate Command
;//                   <i> and a Precharge Command, in cycles
;//     <o0.28..31> TXSR: Exit Self Refresh to Active Delay <0-15>
;//                   <i> Defines delay between SCKE set high
;//                   <i> and an Activate Command, in cycles
;//   </h>
SDRAMC_CR_Val   EQU     0x85227259

;//   <h> High Speed Register (SDRAMC_HSR)
;//     <o0.0>        DA: Decode Cycle Enable
;//   </h>
SDRAMC_HSR_Val  EQU     0x00000000

;// </e> SDRAM Controller (SDRAMC)


;----------------------- Power Management Controller (PMC) Definitions ---------

; Power Management Controller (PMC) definitions
PMC_BASE        EQU     0xFFFFFC00      ; PMC                     Base Address
PMC_SCER_OFS    EQU     0x00            ; Sys Clk Enable Reg      Address Offset
PMC_SCDR_OFS    EQU     0x04            ; Sys Clk Disable Reg     Address Offset
PMC_SCSR_OFS    EQU     0x08            ; Sys Clk Status Reg      Address Offset
PMC_PCER_OFS    EQU     0x10            ; Periph Clk Enable Reg   Address Offset
PMC_PCDR_OFS    EQU     0x14            ; Periph Clk Disable Reg  Address Offset
PMC_PCSR_OFS    EQU     0x18            ; Periph Clk Status Reg   Address Offset
CKGR_MOR_OFS    EQU     0x20            ; Main Oscillator Reg     Address Offset
CKGR_MCFR_OFS   EQU     0x24            ; Main Clock Freq Reg     Address Offset
CKGR_PLLAR_OFS  EQU     0x28            ; PLLA Reg                Address Offset
CKGR_PLLBR_OFS  EQU     0x2C            ; PLLA Reg                Address Offset
PMC_MCKR_OFS    EQU     0x30            ; Master Clock Reg        Address Offset
PMC_ACKR_OFS    EQU     0x34            ; Application Clock Reg   Address Offset
PMC_PCK0_OFS    EQU     0x40            ; Programmable Clk 0 Reg  Address Offset
PMC_PCK1_OFS    EQU     0x44            ; Programmable Clk 1 Reg  Address Offset
PMC_PCK2_OFS    EQU     0x48            ; Programmable Clk 2 Reg  Address Offset
PMC_PCK3_OFS    EQU     0x4C            ; Programmable Clk 3 Reg  Address Offset
PMC_IER_OFS     EQU     0x60            ; Interrupt Enable  Reg   Address Offset
PMC_IDR_OFS     EQU     0x64            ; Interrupt Disable Reg   Address Offset
PMC_SR_OFS      EQU     0x68            ; Status Register         Address Offset
PMC_IMR_OFS     EQU     0x6C            ; Interrupt Mask Reg      Address Offset

; Bit constants
PMC_MOSCEN      EQU     (1<<0)          ; Main Oscillator Enable
PMC_MUL         EQU     (0x7FF<<16)     ; PLL Multiplier
PMC_MOSCS       EQU     (1<<0)          ; Main Oscillator Stable
PMC_LOCKA       EQU     (1<<1)          ; PLL A Lock Status
PMC_LOCKB       EQU     (1<<2)          ; PLL A Lock Status
PMC_MCKRDY      EQU     (1<<3)          ; Master Clock Status

;// <e> Power Management Controller (PMC)
;//   <h> System Clock Enable Register (PMC_SCER)
;//     <o1.0>      PCK: Processor Clock Enable
;//     <o1.1>      UDP: USB Device Port Clock Enable
;//     <o1.2>      MCKUDP: USB Device Port Master Clock Automatic Disable on Suspend Enable
;//     <o1.4>      UHP: USB Host Port Clock Enable
;//     <o1.8>      PCK0: Programmable Clock Output Enable
;//     <o1.9>      PCK1: Programmable Clock Output Enable
;//     <o1.10>     PCK2: Programmable Clock Output Enable
;//     <o1.11>     PCK3: Programmable Clock Output Enable
;//   </h>
;//
;//   <h> Peripheral Clock Enable Register (PMC_PCER)
;//     <o2.2>      PID2: Parallel IO Controller A Enable
;//     <o2.3>      PID3: Parallel IO Controller B Enable
;//     <o2.4>      PID4: Parallel IO Controller C Enable
;//     <o2.5>      PID5: Parallel IO Controller D Enable
;//     <o2.6>      PID6: USART0 Enable
;//     <o2.7>      PID7: USART1 Enable
;//     <o2.8>      PID8: USART2 Enable
;//     <o2.9>      PID9: Multimedia Card Interface Enable
;//     <o2.10>     PID10: USB Device Port Enable
;//     <o2.11>     PID11: Two-Wire Interface Enable
;//     <o2.12>     PID12: Serial Peripheral Interface 0 Enable
;//     <o2.13>     PID13: Serial Peripheral Interface 1 Enable
;//     <o2.14>     PID14: Serial Synchronous Controller 0 Enable
;//     <o2.15>     PID15: Serial Synchronous Controller 1 Enable
;//     <o2.16>     PID16: Serial Synchronous Controller 2 Enable
;//     <o2.17>     PID17: Timer Counter 0 Enable
;//     <o2.18>     PID18: Timer Counter 1 Enable
;//     <o2.19>     PID19: Timer Counter 2 Enable
;//     <o2.20>     PID20: USB Host Port Enable
;//     <o2.21>     PID21: LCD Controller Enable
;//     <o2.29>     PID29: Advanced Interrupt Controller (IRQ0) Enable
;//     <o2.30>     PID30: Advanced Interrupt Controller (IRQ1) Enable
;//     <o2.31>     PID31: Advanced Interrupt Controller (IRQ2) Enable
;//   </h>
;//
;//   <h> Main Oscillator Register (CKGR_MOR)
;//     <o3.0>      MOSCEN: Main Oscillator Enable
;//     <o3.8..15>  OSCOUNT: Main Oscillator Startup Time <0-255>
;//   </h>
;//
;//   <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR)
;//                   <i> PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1)
;//                   <i> Example: XTAL = 18.432 MHz, DIVA = 14, MULA = 72  =>  PLLA = 96.1097 MHz
;//     <o4.0..7>   DIVA: PLL Divider A <0-255>
;//                   <i> 0        - Divider output is 0
;//                   <i> 1        - Divider is bypassed
;//                   <i> 2 .. 255 - Divider output is the Main Clock divided by DIVA
;//     <o4.8..13>  PLLACOUNT: PLL A Counter <0-63>
;//                   <i> Number of Slow Clocks before the LOCKA bit is set in 
;//                   <i> PMC_SR after CKGR_PLLAR is written
;//     <o4.14..15> OUTA: PLL A Clock Frequency Range
;//                   <0=> 80 .. 160MHz   <1=> Reserved
;//                   <2=> 150 .. 240MHz  <3=> Reserved
;//     <o4.16..26> MULA: PLL A Multiplier <0-2047>
;//                   <i> 0         - The PLL A is deactivated
;//                   <i> 1 .. 2047 - The PLL A Clock frequency is the PLL a input 
;//                   <i>             frequency multiplied by MULA + 1
;//   </h>
;//
;//   <h> Clock Generator Phase Locked Loop B Register (CKGR_PLLBR)
;//                   <i> PLL B Freq = (Main CLOCK Freq / DIVB) * (MULB + 1)
;//     <o5.0..7>   DIVB: PLL Divider B <0-255>
;//                   <i> 0        - Divider output is 0
;//                   <i> 1        - Divider is bypassed
;//                   <i> 2 .. 255 - Divider output is the Main Clock divided by DIVB
;//     <o5.8..13>  PLLBCOUNT: PLL B Counter <0-63>
;//                   <i> Number of Slow Clocks before the LOCKB bit is set in 
;//                   <i> PMC_SR after CKGR_PLLBR is written
;//     <o5.14..15> OUTB: PLL B Clock Frequency Range
;//                   <0=> 80 .. 160MHz   <1=> Reserved
;//                   <2=> 150 .. 240MHz  <3=> Reserved
;//     <o5.16..26> MULB: PLL B Multiplier <0-2047>
;//                   <i> 0         - The PLL B is deactivated
;//                   <i> 1 .. 2047 - The PLL B Clock frequency is the PLL a input 
;//                   <i>             frequency multiplied by MULB + 1
;//     <o5.28>     USB_96M: Divider by 2 Enable
;//                   <i> 0 - USB ports = PLL B Clock, PLL B Clock must be 48MHz
;//                   <i> 1 - USB ports = PLL B Clock / 2, PLL B Clock must be 96MHz
;//   </h>
;//
;//   <h> Master Clock Register (CKGR_MCKR)
;//     <o6.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o6.2..4>   PRES: Master Clock Prescaler
;//                   <0=> Clock        <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//     <o6.8..9>   MDIV: Master Clock Division
;//                   <0=> Processor Clock = Master Clock
;//                   <1=> Processor Clock = Master Clock / 2
;//                   <2=> Processor Clock = Master Clock / 3
;//                   <3=> Processor Clock = Master Clock / 4
;//   </h>
;//
;//   <h> Programmable Clock Register 0 (PMC_PCK0)
;//     <o7.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock
;//                   <3=> PLL B Clock
;//     <o7.2..4>   PRES: Programmable Clock Prescaler
;//                   <0=> Clock        <1=> Clock / 2
;//                   <2=> Clock / 4    <3=> Clock / 8
;//                   <4=> Clock / 16   <5=> Clock / 32
;//                   <6=> Clock / 64   <7=> Reserved
;//   </h>
;//
;//   <h> Programmable Clock Register 1 (PMC_PCK1)
;//     <o8.0..1>   CSS: Master Clock Selection
;//                   <0=> Slow Clock
;//                   <1=> Main Clock
;//                   <2=> PLL A Clock