sam9261.s

reference about 9261,refernce tc timer!

;//                     <1=> The write operation is controlled by the NWE signal
;//       <o4.4..5>   EXNW_MODE: NWAIT Mode
;//                     <0=> Disabled
;//                     <2=> Frozen Mode
;//                     <3=> Ready Mode
;//       <o4.8>      BAT: Byte Access Type
;//                     <0=> 0
;//                     <1=> 1
;//                     <i>  0: - Write operation is controlled using: NCS, NWE, NBS0, NBS1, NBS2, NBS3
;//                     <i>     - Read  operation is controlled using: NCS, NRD, NBS0, NBS1, NBS2, NBS3
;//                     <i>  1: - Write operation is controlled using: NCS, NWR0, NWR1, NWR2, NWR3        
;//                     <i>     - Read  operation is controlled using: NCS, NRD
;//       <o4.12..13> DBW: Data Bus Width
;//                     <0=> 8-bit bus
;//                     <1=> 16-bit bus
;//                     <2=> 32-bit bus
;//       <o4.16..19> TDF_CYCLES: Data Float Time <0-15>
;//       <o4.20>     TDF_MODE: TDF Optimization Enabled
;//       <o4.24>     PMEN: Page Mode Enabled
;//       <o4.28..29> PS: Page Size
;//                     <0=> 4-byte page
;//                     <1=> 8-byte page
;//                     <2=> 16-byte page
;//                     <3=> 32-byte page
;//     </h>
;//   </e>
SMC_CS3_SETUP   EQU     0x00000000
SMC_SETUP3_Val  EQU     0x00000000
SMC_PULSE3_Val  EQU     0x01010101
SMC_CYCLE3_Val  EQU     0x00010001
SMC_MODE3_Val   EQU     0x10001000

;//   <e> SMC Chip Select 4 Configuration
;//     <h> Chip Select 4 Setup Register (SMC_SETUP4)
;//       <o1.0..5>   NWE_SETUP: NWE Setup Length <0-31>
;//                     <i> NWE setup length = (128*NWE_SETUP[5]+NWE_SETUP[4..0]) clock cycles
;//       <o1.8..13>  NCS_WR_SETUP: NCS Setup Length in WRITE Access <0-31>
;//                     <i> NCS setup length = (128*NCS_WR_SETUP[5]+NCS_WR_SETUP[4..0]) clock cycles
;//       <o1.16..21> NRD_SETUP: NRD Setup Length <0-31>
;//                     <i> NRD setup length = (128*NRD_SETUP[5]+NRD_SETUP[4..0]) clock cycles
;//       <o1.24..29> NCS_RD_SETUP: NCS Setup Length in READ Access <0-31>
;//                     <i> NCS setup length = (128*NCS_RD_SETUP[5]+NCS_RD_SETUP[4..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 4 Pulse Register (SMC_PULSE4)
;//       <o2.0..6>   NWE_PULSE: NWE Pulse Length <0-63>
;//                     <i> NWE pulse length = (128*NWE_PULSE[6]+NWE_PULSE[5..0]) clock cycles
;//       <o2.8..14>  NCS_WR_PULSE: NCS Pulse Length in WRITE Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_WR_PULSE[6]+NCS_WR_PULSE[5..0]) clock cycles
;//       <o2.16..22> NRD_PULSE: NRD Pulse Length <0-63>
;//                     <i> NRD pulse length = (128*NRD_PULSE[6]+NRD_PULSE[5..0]) clock cycles
;//       <o2.24..30> NCS_RD_PULSE: NCS Pulse Length in READ Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_RD_PULSE[6]+NCS_RD_PULSE[5..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 4 Cycle Register (SMC_CYCLE4)
;//       <o3.0..8>   NWE_CYCLE: Total Write Cycle Length <0-511>
;//                     <i> Write cycle length = (NWE_CYCLE[8..7]*256+NWE_CYCLE[6..0]) clock cycle
;//       <o3.16..24> NRD_CYCLE: Total Read Cycle Length <0-511>
;//                     <i> Read cycle length = (NRD_CYCLE[8..7]*256+NRD_CYCLE[6..0]) clock cycle
;//     </h>
;//
;//     <h> Chip Select 4 Mode Register (SMC_MODE4)
;//       <o4.0>      READ_MODE:
;//                     <0=> The read operation is controlled by the NCS signal
;//                     <1=> The read operation is controlled by the NRD signal
;//       <o4.1>      WRITE_MODE:
;//                     <0=> The write operation is controlled by the NCS signal
;//                     <1=> The write operation is controlled by the NWE signal
;//       <o4.4..5>   EXNW_MODE: NWAIT Mode
;//                     <0=> Disabled
;//                     <2=> Frozen Mode
;//                     <3=> Ready Mode
;//       <o4.8>      BAT: Byte Access Type
;//                     <0=> 0
;//                     <1=> 1
;//                     <i>  0: - Write operation is controlled using: NCS, NWE, NBS0, NBS1, NBS2, NBS3
;//                     <i>     - Read  operation is controlled using: NCS, NRD, NBS0, NBS1, NBS2, NBS3
;//                     <i>  1: - Write operation is controlled using: NCS, NWR0, NWR1, NWR2, NWR3        
;//                     <i>     - Read  operation is controlled using: NCS, NRD
;//       <o4.12..13> DBW: Data Bus Width
;//                     <0=> 8-bit bus
;//                     <1=> 16-bit bus
;//                     <2=> 32-bit bus
;//       <o4.16..19> TDF_CYCLES: Data Float Time <0-15>
;//       <o4.20>     TDF_MODE: TDF Optimization Enabled
;//       <o4.24>     PMEN: Page Mode Enabled
;//       <o4.28..29> PS: Page Size
;//                     <0=> 4-byte page
;//                     <1=> 8-byte page
;//                     <2=> 16-byte page
;//                     <3=> 32-byte page
;//     </h>
;//   </e>
SMC_CS4_SETUP   EQU     0x00000000
SMC_SETUP4_Val  EQU     0x00000000
SMC_PULSE4_Val  EQU     0x01010101
SMC_CYCLE4_Val  EQU     0x00010001
SMC_MODE4_Val   EQU     0x10001000

;//   <e> SMC Chip Select 5 Configuration
;//     <h> Chip Select 5 Setup Register (SMC_SETUP5)
;//       <o1.0..5>   NWE_SETUP: NWE Setup Length <0-31>
;//                     <i> NWE setup length = (128*NWE_SETUP[5]+NWE_SETUP[4..0]) clock cycles
;//       <o1.8..13>  NCS_WR_SETUP: NCS Setup Length in WRITE Access <0-31>
;//                     <i> NCS setup length = (128*NCS_WR_SETUP[5]+NCS_WR_SETUP[4..0]) clock cycles
;//       <o1.16..21> NRD_SETUP: NRD Setup Length <0-31>
;//                     <i> NRD setup length = (128*NRD_SETUP[5]+NRD_SETUP[4..0]) clock cycles
;//       <o1.24..29> NCS_RD_SETUP: NCS Setup Length in READ Access <0-31>
;//                     <i> NCS setup length = (128*NCS_RD_SETUP[5]+NCS_RD_SETUP[4..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 5 Pulse Register (SMC_PULSE5)
;//       <o2.0..6>   NWE_PULSE: NWE Pulse Length <0-63>
;//                     <i> NWE pulse length = (128*NWE_PULSE[6]+NWE_PULSE[5..0]) clock cycles
;//       <o2.8..14>  NCS_WR_PULSE: NCS Pulse Length in WRITE Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_WR_PULSE[6]+NCS_WR_PULSE[5..0]) clock cycles
;//       <o2.16..22> NRD_PULSE: NRD Pulse Length <0-63>
;//                     <i> NRD pulse length = (128*NRD_PULSE[6]+NRD_PULSE[5..0]) clock cycles
;//       <o2.24..30> NCS_RD_PULSE: NCS Pulse Length in READ Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_RD_PULSE[6]+NCS_RD_PULSE[5..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 5 Cycle Register (SMC_CYCLE5)
;//       <o3.0..8>   NWE_CYCLE: Total Write Cycle Length <0-511>
;//                     <i> Write cycle length = (NWE_CYCLE[8..7]*256+NWE_CYCLE[6..0]) clock cycle
;//       <o3.16..24> NRD_CYCLE: Total Read Cycle Length <0-511>
;//                     <i> Read cycle length = (NRD_CYCLE[8..7]*256+NRD_CYCLE[6..0]) clock cycle
;//     </h>
;//
;//     <h> Chip Select 5 Mode Register (SMC_MODE5)
;//       <o4.0>      READ_MODE:
;//                     <0=> The read operation is controlled by the NCS signal
;//                     <1=> The read operation is controlled by the NRD signal
;//       <o4.1>      WRITE_MODE:
;//                     <0=> The write operation is controlled by the NCS signal
;//                     <1=> The write operation is controlled by the NWE signal
;//       <o4.4..5>   EXNW_MODE: NWAIT Mode
;//                     <0=> Disabled
;//                     <2=> Frozen Mode
;//                     <3=> Ready Mode
;//       <o4.8>      BAT: Byte Access Type
;//                     <0=> 0
;//                     <1=> 1
;//                     <i>  0: - Write operation is controlled using: NCS, NWE, NBS0, NBS1, NBS2, NBS3
;//                     <i>     - Read  operation is controlled using: NCS, NRD, NBS0, NBS1, NBS2, NBS3
;//                     <i>  1: - Write operation is controlled using: NCS, NWR0, NWR1, NWR2, NWR3        
;//                     <i>     - Read  operation is controlled using: NCS, NRD
;//       <o4.12..13> DBW: Data Bus Width
;//                     <0=> 8-bit bus
;//                     <1=> 16-bit bus
;//                     <2=> 32-bit bus
;//       <o4.16..19> TDF_CYCLES: Data Float Time <0-15>
;//       <o4.20>     TDF_MODE: TDF Optimization Enabled
;//       <o4.24>     PMEN: Page Mode Enabled
;//       <o4.28..29> PS: Page Size
;//                     <0=> 4-byte page
;//                     <1=> 8-byte page
;//                     <2=> 16-byte page
;//                     <3=> 32-byte page
;//     </h>
;//   </e>
SMC_CS5_SETUP   EQU     0x00000000
SMC_SETUP5_Val  EQU     0x00000000
SMC_PULSE5_Val  EQU     0x01010101
SMC_CYCLE5_Val  EQU     0x00010001
SMC_MODE5_Val   EQU     0x10001000

;//   <e> SMC Chip Select 6 Configuration
;//     <h> Chip Select 6 Setup Register (SMC_SETUP6)
;//       <o1.0..5>   NWE_SETUP: NWE Setup Length <0-31>
;//                     <i> NWE setup length = (128*NWE_SETUP[5]+NWE_SETUP[4..0]) clock cycles
;//       <o1.8..13>  NCS_WR_SETUP: NCS Setup Length in WRITE Access <0-31>
;//                     <i> NCS setup length = (128*NCS_WR_SETUP[5]+NCS_WR_SETUP[4..0]) clock cycles
;//       <o1.16..21> NRD_SETUP: NRD Setup Length <0-31>
;//                     <i> NRD setup length = (128*NRD_SETUP[5]+NRD_SETUP[4..0]) clock cycles
;//       <o1.24..29> NCS_RD_SETUP: NCS Setup Length in READ Access <0-31>
;//                     <i> NCS setup length = (128*NCS_RD_SETUP[5]+NCS_RD_SETUP[4..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 6 Pulse Register (SMC_PULSE6)
;//       <o2.0..6>   NWE_PULSE: NWE Pulse Length <0-63>
;//                     <i> NWE pulse length = (128*NWE_PULSE[6]+NWE_PULSE[5..0]) clock cycles
;//       <o2.8..14>  NCS_WR_PULSE: NCS Pulse Length in WRITE Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_WR_PULSE[6]+NCS_WR_PULSE[5..0]) clock cycles
;//       <o2.16..22> NRD_PULSE: NRD Pulse Length <0-63>
;//                     <i> NRD pulse length = (128*NRD_PULSE[6]+NRD_PULSE[5..0]) clock cycles
;//       <o2.24..30> NCS_RD_PULSE: NCS Pulse Length in READ Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_RD_PULSE[6]+NCS_RD_PULSE[5..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 6 Cycle Register (SMC_CYCLE6)
;//       <o3.0..8>   NWE_CYCLE: Total Write Cycle Length <0-511>
;//                     <i> Write cycle length = (NWE_CYCLE[8..7]*256+NWE_CYCLE[6..0]) clock cycle
;//       <o3.16..24> NRD_CYCLE: Total Read Cycle Length <0-511>
;//                     <i> Read cycle length = (NRD_CYCLE[8..7]*256+NRD_CYCLE[6..0]) clock cycle
;//     </h>
;//
;//     <h> Chip Select 6 Mode Register (SMC_MODE6)
;//       <o4.0>      READ_MODE:
;//                     <0=> The read operation is controlled by the NCS signal
;//                     <1=> The read operation is controlled by the NRD signal
;//       <o4.1>      WRITE_MODE:
;//                     <0=> The write operation is controlled by the NCS signal
;//                     <1=> The write operation is controlled by the NWE signal
;//       <o4.4..5>   EXNW_MODE: NWAIT Mode
;//                     <0=> Disabled
;//                     <2=> Frozen Mode
;//                     <3=> Ready Mode
;//       <o4.8>      BAT: Byte Access Type
;//                     <0=> 0
;//                     <1=> 1
;//                     <i>  0: - Write operation is controlled using: NCS, NWE, NBS0, NBS1, NBS2, NBS3
;//                     <i>     - Read  operation is controlled using: NCS, NRD, NBS0, NBS1, NBS2, NBS3
;//                     <i>  1: - Write operation is controlled using: NCS, NWR0, NWR1, NWR2, NWR3        
;//                     <i>     - Read  operation is controlled using: NCS, NRD
;//       <o4.12..13> DBW: Data Bus Width
;//                     <0=> 8-bit bus
;//                     <1=> 16-bit bus
;//                     <2=> 32-bit bus
;//       <o4.16..19> TDF_CYCLES: Data Float Time <0-15>
;//       <o4.20>     TDF_MODE: TDF Optimization Enabled
;//       <o4.24>     PMEN: Page Mode Enabled
;//       <o4.28..29> PS: Page Size
;//                     <0=> 4-byte page
;//                     <1=> 8-byte page
;//                     <2=> 16-byte page
;//                     <3=> 32-byte page
;//     </h>
;//   </e>
SMC_CS6_SETUP   EQU     0x00000000
SMC_SETUP6_Val  EQU     0x00000000
SMC_PULSE6_Val  EQU     0x01010101
SMC_CYCLE6_Val  EQU     0x00010001
SMC_MODE6_Val   EQU     0x10001000

;//   <e> SMC Chip Select 7 Configuration
;//     <h> Chip Select 7 Setup Register (SMC_SETUP7)
;//       <o1.0..5>   NWE_SETUP: NWE Setup Length <0-31>
;//                     <i> NWE setup length = (128*NWE_SETUP[5]+NWE_SETUP[4..0]) clock cycles
;//       <o1.8..13>  NCS_WR_SETUP: NCS Setup Length in WRITE Access <0-31>
;//                     <i> NCS setup length = (128*NCS_WR_SETUP[5]+NCS_WR_SETUP[4..0]) clock cycles
;//       <o1.16..21> NRD_SETUP: NRD Setup Length <0-31>
;//                     <i> NRD setup length = (128*NRD_SETUP[5]+NRD_SETUP[4..0]) clock cycles
;//       <o1.24..29> NCS_RD_SETUP: NCS Setup Length in READ Access <0-31>
;//                     <i> NCS setup length = (128*NCS_RD_SETUP[5]+NCS_RD_SETUP[4..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 7 Pulse Register (SMC_PULSE7)
;//       <o2.0..6>   NWE_PULSE: NWE Pulse Length <0-63>
;//                     <i> NWE pulse length = (128*NWE_PULSE[6]+NWE_PULSE[5..0]) clock cycles
;//       <o2.8..14>  NCS_WR_PULSE: NCS Pulse Length in WRITE Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_WR_PULSE[6]+NCS_WR_PULSE[5..0]) clock cycles
;//       <o2.16..22> NRD_PULSE: NRD Pulse Length <0-63>
;//                     <i> NRD pulse length = (128*NRD_PULSE[6]+NRD_PULSE[5..0]) clock cycles
;//       <o2.24..30> NCS_RD_PULSE: NCS Pulse Length in READ Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_RD_PULSE[6]+NCS_RD_PULSE[5..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 7 Cycle Register (SMC_CYCLE7)
;//       <o3.0..8>   NWE_CYCLE: Total Write Cycle Length <0-511>
;//                     <i> Write cycle length = (NWE_CYCLE[8..7]*256+NWE_CYCLE[6..0]) clock cycle