debug.c

网络驱动开发

       }

       DbgPrint("(%d) %lx, ", i, (PhData&0xFFFF));

   }

	DbgPrint("\n<==dbgDumpAtm155EntryOfRxStat.\n");

}


VOID
dbgDumpAtm155TableSram(
	IN  PADAPTER_BLOCK      pAdapter,
   IN  ULONG               StartDest,
   IN  ULONG               EndDest
	)
/*++

Routine Description:

	This routine dumps the table on ATM 155 on-board SRAM.

Arguments:

	pAdapter    -   Pointer to ADAPTER memory block.

Return Value:

	None.

--*/
{
   NDIS_STATUS     Status;
   ULONG           Dest;
   ULONG           PhData;

   for (Dest = StartDest; Dest < EndDest; Dest++)
   {
       if (!(Dest & 0x07))
       {
           if (!(Dest & 0x0ff))
           {
               // just for setting break point.
	            DbgPrint("\n");
	            DbgPrint("%lx: ", Dest);
           }
           else
           {
	            DbgPrint("\n%lx: ", Dest);
           }
       }

       TBATM155_PH_READ_SRAM(pAdapter, Dest, &PhData, &Status);

       if (NDIS_STATUS_SUCCESS != Status)
       {
	        DBGPRINT(DBG_COMP_VC, DBG_LEVEL_ERR,
		        ("Failed to open the entry the table.\n") );

           break;
       }

       DbgPrint("%lx, ", (PhData&0xFFFF));

   }

}



VOID
dbgDumpAtm155Sram_1KVcs(
	IN  PADAPTER_BLOCK      pAdapter
	)
/*++

Routine Description:

	This routine dumps ATM 155 on-board SRAM supported up to 1K VCs.

Arguments:

	pAdapter    -   Pointer to ADAPTER memory block.

Return Value:

	None.

--*/
{
   PHARDWARE_INFO      pHwInfo = pAdapter->HardwareInfo;
   PSRAM_1K_VC_MODE     pSramAddrTbl;
   

	DbgPrint("==>dbgDumpAtm155Sram_1KVcs.\n");

   pSramAddrTbl = (PSRAM_1K_VC_MODE)pHwInfo->pSramAddrTbl;
   
	DbgPrint("Rx AAL5 big Free slot FIFO:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_AAL5_Big_Free_Slot,
       pSramAddrTbl->pRx_AAL5_Small_Free_Slot
       );


	DbgPrint("\nRx AAL5 small Free slot FIFO:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_AAL5_Small_Free_Slot,
       pSramAddrTbl->pRx_Raw_Free_Slot
       );

	DbgPrint("\nRx AAL5 raw Free slot FIFO:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_Raw_Free_Slot,
       pSramAddrTbl->pReserved1
       );

	DbgPrint("\nRx Vc State table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_VC_State_Tbl,
       pSramAddrTbl->pTx_VC_State_Tbl
       );

	DbgPrint("\nTx Vc State table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pTx_VC_State_Tbl,
       pSramAddrTbl->pABR_Parameter_Tbl
       );

	DbgPrint("\nABR parameter table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pABR_Parameter_Tbl,
       pSramAddrTbl->pABR_Value_Tbl
       );

	DbgPrint("\nABR value table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pABR_Value_Tbl,
       pSramAddrTbl->pRM_Cell_Data_Tbl
       );

	DbgPrint("\nRM cell table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRM_Cell_Data_Tbl,
       pSramAddrTbl->pTx_Slot_Descriptors
       );

	DbgPrint("\nTx slot descriptor table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pTx_Slot_Descriptors,
       pSramAddrTbl->pACR_LookUp_Tbl
       );

	DbgPrint("\nACR lookup table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pACR_LookUp_Tbl,
       pSramAddrTbl->pReserved2
       );

	DbgPrint("\nABR schedule table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pABR_Schedule_Tbl,
       pSramAddrTbl->pCBR_Schedule_Tbl_1
       );

	DbgPrint("\nCBR schedule table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pCBR_Schedule_Tbl_1,
       pSramAddrTbl->pEnd_Of_SRAM
       );


	DbgPrint("<==dbgDumpAtm155Sram_1KVcs.\n");

}




VOID
dbgDumpAtm155Sram_4KVcs(
	IN  PADAPTER_BLOCK      pAdapter
	)
/*++

Routine Description:

	This routine dumps ATM 155 on-board SRAM supported up to 4K VCs.

Arguments:

	pAdapter    -   Pointer to ADAPTER memory block.

Return Value:

	None.

--*/
{
   PHARDWARE_INFO      pHwInfo = pAdapter->HardwareInfo;
   PSRAM_4K_VC_MODE     pSramAddrTbl;
   

	DbgPrint("==>dbgDumpAtm155Sram_4KVcs.\n");

   pSramAddrTbl = (PSRAM_4K_VC_MODE)pHwInfo->pSramAddrTbl;
   
	DbgPrint("Rx AAL5 big Free slot FIFO:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_AAL5_Big_Free_Slot,
       pSramAddrTbl->pRx_AAL5_Small_Free_Slot
       );


	DbgPrint("\nRx AAL5 small Free slot FIFO:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_AAL5_Small_Free_Slot,
       pSramAddrTbl->pRx_Raw_Free_Slot
       );

	DbgPrint("\nRx AAL5 raw Free slot FIFO:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_Raw_Free_Slot,
       pSramAddrTbl->pACR_LookUp_Tbl
       );

	DbgPrint("\nACR lookup table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pACR_LookUp_Tbl,
       pSramAddrTbl->pReserved
       );

	DbgPrint("\nRx Vc State table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_VC_State_Tbl,
       pSramAddrTbl->pTx_VC_State_Tbl
       );

	DbgPrint("\nTx Vc State table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pTx_VC_State_Tbl,
       pSramAddrTbl->pABR_Parameter_Tbl
       );

	DbgPrint("\nABR parameter table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pABR_Parameter_Tbl,
       pSramAddrTbl->pABR_Value_Tbl
       );

	DbgPrint("\nABR value table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pABR_Value_Tbl,
       pSramAddrTbl->pRM_Cell_Data_Tbl
       );

	DbgPrint("\nRM cell table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRM_Cell_Data_Tbl,
       pSramAddrTbl->pTx_Slot_Descriptors
       );

	DbgPrint("\nTx slot descriptor table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pTx_Slot_Descriptors,
       pSramAddrTbl->pABR_Schedule_Tbl
       );


	DbgPrint("\nABR schedule table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pABR_Schedule_Tbl,
       pSramAddrTbl->pCBR_Schedule_Tbl_1
       );

	DbgPrint("\nCBR schedule table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pCBR_Schedule_Tbl_1,
       pSramAddrTbl->pRx_AAL5_B_Slot_Tags
       );

	DbgPrint("\nRx AAL5 Big Slot Tags Table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_AAL5_B_Slot_Tags,
       pSramAddrTbl->pRx_AAL5_S_Slot_Tags
       );

	DbgPrint("\nRx AAL5 Small Slot Tags Table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_AAL5_S_Slot_Tags,
       pSramAddrTbl->pRx_Raw_Slot_Tags
       );

	DbgPrint("\nRx AAL5 Raw Slot Tags Table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_Raw_Slot_Tags,
       pSramAddrTbl->pRx_Slot_Tag_VC_State_Tbl
       );

	DbgPrint("\nRx Slot Tag VC State Table:\n");
   dbgDumpAtm155TableSram(
       pAdapter, 
       pSramAddrTbl->pRx_Slot_Tag_VC_State_Tbl,
       pSramAddrTbl->pEnd_Of_SRAM 
       );


	DbgPrint("<==dbgDumpAtm155Sram_4KVcs.\n");

}


#endif	// DBG


#if DBG_USING_LED
VOID
dbgSetLED(
	IN  PADAPTER_BLOCK      pAdapter,
	IN  UCHAR               SetLedValue,
	IN  UCHAR               MaskLedValue
	)
/*++

Routine Description:

	This routine sets LED for debugging time sensitive
   issues.

Arguments:

	pAdapter        -   Pointer to ADAPTER memory block.
	SetLedValue     -   LED setting
	MaskLedValue    -   Mask the current LED setting

Return Value:

	None.

--*/
{
   PHARDWARE_INFO      pHwInfo = pAdapter->HardwareInfo;
   NDIS_STATUS         Status;
   
   NdisAcquireSpinLock(&pHwInfo->Lock);
   pHwInfo->dbgLedVal = (pHwInfo->dbgLedVal & MaskLedValue) | SetLedValue;
   NdisReleaseSpinLock(&pHwInfo->Lock);

   TBATM155_PH_WRITE_DEV(pAdapter, LED_OFFSET, pHwInfo->dbgLedVal, &Status);
}


#endif // end of DBG_USING_LED



#if TB_DBG

VOID
dbgProcXmitDmaWaitQ(
   IN  PADAPTER_BLOCK  pAdapter
   )

/*++

Routine Description:

   This routine will either queue a packet to the transmit DMA queue or
   DMA the packet.

Arguments:

   pAdapter    -   Pointer to the ADAPTER_BLOCK

Return Value:

   NDIS_STATUS_SUCCESS if the packet was successfully sent to the
                       transmit DMA engine.
   NDIS_STATUS_PENDING if it was queued waiting for DMA resources.

--*/
{
   PSAR_INFO           pSar = pAdapter->HardwareInfo->SarInfo;
   PXMIT_DMA_QUEUE     pXmitDmaQ = &pSar->XmitDmaQ;
   PNDIS_PACKET        tmpPacket;
   PPACKET_RESERVED    Reserved;
   PXMIT_SEG_INFO      pXmitSegInfo;
   PVC_BLOCK           pVc;


   //
   //	If a packet was not passed in to transmit then we need to
   //	grab them off of the pending queue.
   //
   NdisAcquireSpinLock(&pXmitDmaQ->lock);

   //
   //	Loop through the packets that are waiting for dma resources.
   //
   while (!PACKET_QUEUE_EMPTY(&pXmitDmaQ->DmaWait))
   {
       //
       //	Are there enough resources to process the
       //	packet?
       //
       Reserved = PACKET_RESERVED_FROM_PACKET(pXmitDmaQ->DmaWait.Head);
       pVc = Reserved->pVc;
       pXmitSegInfo = pVc->XmitSegInfo;
       RemovePacketFromHead(&pXmitDmaQ->DmaWait, &tmpPacket);

       DbgPrint("dbgProcXmitDmaWaitQ(Vc:0x%lx)\n", pVc->VpiVci.Vci);

       if (pXmitSegInfo->FreePadTrailerBuffers == 0)
       {
           NdisMCoSendComplete(
               NDIS_STATUS_REQUEST_ABORTED,
               pVc->NdisVcHandle,
               tmpPacket);

           continue;
       }

       if (pXmitDmaQ->RemainingTransmitSlots < Reserved->PhysicalBufferCount)
       {
           NdisMCoSendComplete(
               NDIS_STATUS_REQUEST_ABORTED,
               pVc->NdisVcHandle,
               tmpPacket);

           continue;
       }

       DbgPrint("dbgProcXmitDmaWaitQ(Vc:0x%lx) is calling tbAtm155TransmitPacket\n", 
                pVc->VpiVci.Vci);

       //
       //	Transmit the packet.
       //
       tbAtm155TransmitPacket(pVc, tmpPacket);

   }

   NdisReleaseSpinLock(&pXmitDmaQ->lock);

} // end of dbgProcXmitDmaWaitQ


VOID
dbgDumpActivateVcInfo(
	IN  PADAPTER_BLOCK      pAdapter
	)
/*++

Routine Description:

	This routine displays info of VCs by going through the activate VC table
   issues.

Arguments:

	pAdapter        -   Pointer to ADAPTER memory block.

Return Value:

	None.

--*/
{
   PLIST_ENTRY         Link;
   PVC_BLOCK           pVc;
   PXMIT_SEG_INFO      pXmitSegInfo;
   PXMIT_DMA_QUEUE     pXmitDmaQ = &pAdapter->HardwareInfo->SarInfo->XmitDmaQ;


   if (DBG_PENDING_PKTS == (gTbAtm155DebugSystems & DBG_PENDING_PKTS))
   {
       //
       //	Walk through the VC's that are opened on this adapter and mark
       //	them out of resetting. Also check to see if any VCs need to 
       //  be deactivated.
       //
       DbgPrint("pAdapter->ActiveVcList:\n");
       for (Link = pAdapter->ActiveVcList.Flink;
            Link != &pAdapter->ActiveVcList;
            Link = Link->Flink)
       {
           //
           //	Get a pointer to the VC that link represents.
           //
           pVc = CONTAINING_RECORD(Link, VC_BLOCK, Link);
           
           NdisAcquireSpinLock(&pVc->lock);
           
           DbgPrint("Vc(0x%lx), VcRef:(%u), VcFlags:(0x%lx), pVc("PTR_FORMAT")\n", 
                     pVc->VpiVci.Vci, pVc->References, pVc->Flags, pVc);

           if (VC_TEST_FLAG(pVc, fVC_TRANSMIT))
           {
               pXmitSegInfo = pVc->XmitSegInfo;
               DbgPrint("DmaCompleting.Ref:(%u)\n", pXmitSegInfo->DmaCompleting.References);
               DbgPrint("SegWait.Ref:(%u)\n", pXmitSegInfo->SegWait.References);
               DbgPrint("FreePadTrailerBufs:(%u), BeOrBeingUsedPadTrailerBufs:(%u)\n", 
                         pXmitSegInfo->FreePadTrailerBuffers, pXmitSegInfo->BeOrBeingUsedPadTrailerBufs);
           }
           
           NdisReleaseSpinLock(&pVc->lock);

       }

       DbgPrint("pAdapter->InactiveVcList:\n");
       for (Link = pAdapter->InactiveVcList.Flink;
            Link != &pAdapter->InactiveVcList;
            Link = Link->Flink)
       {
           //
           //	Get a pointer to the VC that link represents.
           //
           pVc = CONTAINING_RECORD(Link, VC_BLOCK, Link);
           
           NdisAcquireSpinLock(&pVc->lock);
           
           DbgPrint("Vc(0x%lx), VcRef:(%u), VcFlags:(0x%lx), pVc("PTR_FORMAT")\n", 
                     pVc->VpiVci.Vci, pVc->References, pVc->Flags, pVc);

           NdisReleaseSpinLock(&pVc->lock);

       }

       NdisAcquireSpinLock(&pXmitDmaQ->lock);
       DbgPrint("RemainingTransmitSlots:(%u)\n", pXmitDmaQ->RemainingTransmitSlots);
       DbgPrint("DmaWait.Ref:(%u), AdapterFlags(0x%lx)\n\n", 
                pXmitDmaQ->DmaWait.References, pAdapter->Flags);
       NdisReleaseSpinLock(&pXmitDmaQ->lock);

   } // end of if
    
   if (DBG_XMIT_PKTS == (gTbAtm155DebugSystems & DBG_XMIT_PKTS))
   {
       dbgProcXmitDmaWaitQ(pAdapter);
   }

} 

    
#endif // end of TB_DBG