vc.c

网络驱动开发

           }

           pAddr += (ULONG) Curr_CI;
           if (pAddr > pEndCbrTbl)
           {
               //
               // wrap around. But we should never get into this case.
               //
               pAddr = pEntryAddr_1st + (CellInterval / 2);
           }       

       } // end of FOR 

       if (NDIS_STATUS_SUCCESS != Status)
       {
           break;
       }
   
   } while (FALSE);

   if (NDIS_STATUS_SUCCESS == Status)
   {
       do
       {
           //
           // Set EOT to the CBR table now.
           //
           TBATM155_PH_READ_SRAM(pAdapter, pEndCbrTbl, &phData.data, &Status);
           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Failed rd CBR Schedule table (copy)! \n"));
               break;
           }

           phData.EOT = 1;
       
           TBATM155_PH_WRITE_SRAM(pAdapter, pEndCbrTbl, phData.data, &Status);
           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Failed wr CBR Schedule table (Add more Entries)! \n"));
               break;
           }

           //
           // Select to the new setup CBR schedule table.
           //
           TBATM155_WRITE_PORT(
               &pHwInfo->TbAtm155_SAR->SAR_Cntrl1,
               regControl1.reg);

       } while (FALSE);

   }

   DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO, 
               ("<==tbAtm155SetCbrTblsInSRAM (Status: 0x%lx)\n", Status));

   return(Status);
}


NDIS_STATUS
tbAtm155SetUbrTblsInSRAM(
   IN  PADAPTER_BLOCK  pAdapter,
   IN  PVC_BLOCK       pVc
	)
/*++

Routine Description:

   This routine will setup the tables for UBR flow on on-board SRAM.

Arguments:

   pAdapter    -   Pointer to the adapter to program.
   pVc         -   Pointer to the VC_BLOCK that describes the VC we
                   are handling.

Return Value:

   NDIS_STATUS_SUCCESS     if the entry of VC state table is opened
                           successfully.

--*/
{
   PHARDWARE_INFO          pHwInfo = pAdapter->HardwareInfo;
   NDIS_STATUS             Status = NDIS_STATUS_SUCCESS;
   PATM_FLOW_PARAMETERS    pXmitFlow = &pVc->Transmit;
   ULONG                   rate_FP = 0;

   DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO, 
               ("==>tbAtm155SetUbrTblsInSRAM\n"));

   do
   {
       //
       // Set PCR for UBR to Word0.Acr field.
       // Convert PCR to Floating Point.
       // 
       tbAtm155ConvertToFP(&pXmitFlow->PeakCellRate, &(USHORT)rate_FP);

       TBATM155_PH_WRITE_SRAM(
           pAdapter,
           (pHwInfo->pSramAbrValueTbl + (pVc->VpiVci.Vci * SIZEOF_ABR_VALUE_ENTRY)),
           (ULONG)rate_FP,
           &Status);

       if (NDIS_STATUS_SUCCESS != Status)
       {
           DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
               ("Failed to write word0.Acr of ABR value table.\n"));
           break;
       }

       TBATM155_PH_WRITE_SRAM(
           pAdapter,
           (pHwInfo->pSramAbrValueTbl + 1 + (pVc->VpiVci.Vci * SIZEOF_ABR_VALUE_ENTRY)),
           0,
           &Status);

       if (NDIS_STATUS_SUCCESS != Status)
       {
           DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
               ("Failed to write word1.Fraction of ABR value table.\n"));
       }

   } while (FALSE);

   DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO, 
               ("<==tbAtm155SetUbrTblsInSRAM (Status: 0x%lx)\n", Status));

   return(Status);
}


NDIS_STATUS
tbAtm155SetAbrTblsInSRAM(
   IN  PADAPTER_BLOCK  pAdapter,
   IN  PVC_BLOCK       pVc
	)
/*++

Routine Description:

   This routine will setup the tables for ABR flow on on-board SRAM.

Arguments:

   pAdapter    -   Pointer to the adapter to program.
   pVc         -   Pointer to the VC_BLOCK that describes the VC we
                   are handling.

Return Value:

   NDIS_STATUS_SUCCESS     if the entry of VC state table is opened
                           successfully.

--*/
{
   NDIS_STATUS             Status = NDIS_STATUS_SUCCESS;


//=================================
#if    ABR_CODE
//=================================

   USHORT                  rate_FP;
   USHORT                  logVal;
   ULONG                   temp;
   ULONG                   phAddr;
   TBATM155_ABR_PARAM_ENTRY    AbrParamEntry;



   DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO, 
               ("==>tbAtm155SetAbrTblsInSRAM\n"));

   do
   {
       //
       //	Verify the low end of the bandwidth
       //
       if (pAdapter->RemainingTransmitBandwidth < pAdapter->MinimumAbrBandwidth)
       {
           DBGPRINT(DBG_COMP_VC, DBG_LEVEL_ERR,
               ("There is not enough remaining bandwidth to support even the minimum required bandwidth\n"));

           Status = NDIS_STATUS_FAILURE;
           break;
       }

       //
       //	Make sure we can satisfy the minimum cell rate.
       //
       if (pFlow->PeakCellRate < pAdapter->pAdapter->MinimumAbrBandwidth)
           pFlow->PeakCellRate = pAdapter->pAdapter->MinimumAbrBandwidth;

       if ((pFlow->MinimumCellRate > pAdapter->RemainingTransmitBandwidth) ||
           (pFlow->MinimumCellRate < pAdapter->MinimumAbrBandwidth))
       {
           DBGPRINT(DBG_COMP_VC, DBG_LEVEL_ERR,
               ("CellRate is not within remaining and minimum\n"));

           Status = NDIS_STATUS_FAILURE;
           break;
       }

       if ((pFlow->MissingRMCellCount < TBATM155_MINIMUM_CRM) || 
           (pFlow->MissingRMCellCount > TBATM155_MAXIMUM_CRM))
       {
           DBGPRINT(DBG_COMP_VC, DBG_LEVEL_ERR,
               ("Missing RM cell count is not in range.\n"));

           Status = NDIS_STATUS_FAILURE;
           break;
       }

       //
       // Get the log value of Crm
       //
       for (logVal = 0, temp = 2;
            logVal <= TBATM155_MAXIMUM_LOG_CRMX;
            logVal++, temp *= 2)
       {
           if (temp <= pFlow->MissingRMCellCount)
           {
               // BINGO!!
               break;
           }
       }

       NdisZeroMemory (
           (PVOID)(&AbrParamEntry),
           sizeof(TBATM155_ABR_PARAM_ENTRY));

       AbrParamEntry.AbrParamW0.Crmx = logVal;
       AbrParamEntry.AbrParamW0.RDFx = pFlow->RateDecreaseFactor;
       AbrParamEntry.AbrParamW0.CDFx = pFlow->CutoffDecreaseFactor;

       // 
       // Convert PCR to Floating Point.
       // 
       temp = (ULONG)(pFlow->PeakCellRate * pFlow->RateIncreaseFactor);
       tbAtm155ConvertToFP(&temp, &rate_FP);
       AbrParamEntry.AbrParamW1.AIR = rate_FP;

       tbAtm155ConvertToFP(&pFlow->InitialCellRate, &rate_FP);
       AbrParamEntry.AbrParamW2.ICR = rate_FP;

       tbAtm155ConvertToFP(&pFlow->MinimumCellRate, &rate_FP);
       AbrParamEntry.AbrParamW3.MCR = rate_FP;

       tbAtm155ConvertToFP(&pFlow->PeakCellRate, &rate_FP);
       AbrParamEntry.AbrParamW4.PeakCellRate = rate_FP;

       //
       // Calculate the starting address of the entry for the ABR VC
       //
       phAddr = pHwInfo->pABR_Parameter_Tbl +
                        (pVc->VpiVci.Vci * SIZEOF_ABR_PARAM_ENTRY);


       //
       //  Set the entry of Tx Vc State table.
       //
       Status = tbAtm155WriteEntryOfTheSramTbl(
                   pAdapter,
                   phAddr,
                   (PUSHORT)&AbrParamEntry,
                   SIZEOF_ABR_PARAM_ENTRY);

	    if (NDIS_STATUS_SUCCESS != Status)
       {
           DBGPRINT(DBG_COMP_VC, DBG_LEVEL_ERR,
               ("Failed to fill the entry in ABR parameter table in SRAM.\n"));

           break;
       }

   } while (FALSE);


   DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO, 
               ("<==tbAtm155SetAbrTblsInSRAM (Status: 0x%lx)\n", Status));

   return(Status);



//=================================
#else     // not ABR_CODE
//=================================


   UNREFERENCED_PARAMETER(pAdapter);
   UNREFERENCED_PARAMETER(pVc);

   DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO, 
               ("==>tbAtm155SetAbrTblsInSRAM\n"));


   DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO, 
               ("<==tbAtm155SetAbrTblsInSRAM (Status: 0x%lx)\n", Status));

   return(Status);

//=================================
#endif     // end of ABR_CODE
//=================================

}


VOID
tbAtm155FreeReceiveSegment(
   IN  PVC_BLOCK       pVc
   )
/*++

Routine Description:

   This routine will clean up a receive segment that was (partially)
   allocated.

Arguments:

   pVc -   Pointer to the VC_BLOCK that the receive segment belongs to.

Return Value:

   None.

--*/
{
   PADAPTER_BLOCK          pAdapter = pVc->Adapter;
   PHARDWARE_INFO	        pHwInfo = pVc->HwInfo;
   PRECV_SEG_INFO	        pRecvSegInfo;
   NDIS_STATUS             Status;
   PRECV_BUFFER_QUEUE      pFreeBufQ;

   //
   //	Did we get a receive segment allocated?
   //
   if (NULL != pVc->RecvSegInfo)
   {
       pRecvSegInfo = pVc->RecvSegInfo;

#if   DBG
       if (NULL != pRecvSegInfo->SegCompleting.BufListHead)
       {
           DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
           ("There are still Rx buffer queued in the list.\n"));
           DBGBREAK(DBG_COMP_VC, DBG_LEVEL_ERR);
       }
#endif    // end of DBG

       if (pRecvSegInfo->pEntryOfRecvState)
       {
           //
           //  Clear Open flag of the VC entry in Rx State table
           //  in SRAM to indicate that VC has been closed by the driver.
           //

           pRecvSegInfo->InitRecvState.RxStateWord0.Open = 0;

           TBATM155_PH_WRITE_SRAM(
               pAdapter,
               pRecvSegInfo->pEntryOfRecvState,
               pRecvSegInfo->InitRecvState.RxStateWord0.data,
               &Status);

           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_VC, DBG_LEVEL_INFO,
                   ("Failed to close the VC in the Rx VC State table in SRAM.\n"));
           }
       }

       //
       //  Check if any Rx buffers are pending for this Vc
       //
       if (NULL != pRecvSegInfo->SegCompleting.BufListHead)
       {
           //
           //  Free up the pending Rx buffer(s) to Free list.
           //
           pFreeBufQ = &pHwInfo->SarInfo->FreeBigBufferQ;
           if (pVc->RecvBufType == RECV_SMALL_BUFFER)
           {
               pFreeBufQ = &pHwInfo->SarInfo->FreeSmallBufferQ;
           }

           tbAtm155MergeRecvBuffers2FreeBufferQueue(
                   pAdapter,
                   pFreeBufQ,
                   &pRecvSegInfo->SegCompleting);
       }

       //
       //	Free the receive buffer information.
       //
       if (NULL != pRecvSegInfo->pRecvBufferInfo)
       {
           tbAtm155FreeReceiveBufferInfo(
               pVc->Adapter,
               pRecvSegInfo->pRecvBufferInfo);
       }

       NdisFreeSpinLock(&pRecvSegInfo->lock);
       FREE_MEMORY(pRecvSegInfo, sizeof(RECV_SEG_INFO));
       pVc->RecvSegInfo = NULL;
   }
}


NDIS_STATUS
tbAtm155AllocateReceiveSegment(
   IN  PADAPTER_BLOCK          pAdapter,
   IN  PVC_BLOCK               pVc,
   IN  PATM_MEDIA_PARAMETERS   pAtmMediaParms
   )
/*++

Routine Description:

   This routine will allocate a receive segment for the VC.

Arguments:

   pAdapter        -   Pointer to the ADAPTER_BLOCK.
   pVc             -   Pointer to the VC_BLOCK.
   pAtmMediaParms  -   Pointer to the ATM_MEDIA_PARAMETERS that describe
                       the characteristics of the VC.

Return Value:

   NDIS_STATUS_INVALID_DATA    if the media parameters are incorrect.
   NDIS_STATUS_RESOURCES       if memory cannot be allocated.
   NDIS_STATUS_SUCCESS         if we have successfully allocated and
                               activated the receiver.

--*/
{
   NDIS_STATUS				        Status = NDIS_STATUS_SUCCESS;
   PHARDWARE_INFO			        pHwInfo = pAdapter->HardwareInfo;
   PATM_FLOW_PARAMETERS	        pRecvFlow = &pAtmMediaParms->Receive;
   PSAR_INFO                       pSar = pHwInfo->SarInfo;
   ULONG					        RcvSegmentSize;
   PRECV_SEG_INFO			        pRecvSegInfo = NULL;
   PTBATM155_RX_STATE_ENTRY        pRecvState;
   PTBATM155_REGISTRY_PARAMETER    pRegistryParameters;
   ULONG                           MaxReceiveBufferSize;