tbmeteor.c

网络驱动开发

/*++

Copyright (c) 2000 Microsoft Corporation. All rights reserved.

   File:       tbmeteor.c
 
               Developed for Toshiba by Elisa Research Inc., CA
               http://www.elisaresearch.com
               [phone]


Abstract:

   This file contains routines of Toshiba ATM155 Meteor
   specific handling,
   1. Auto-detecting of the Meteor 1K (or 4K) suppoorting.
   2. Setup the database and then initialize accordingly.


Author:

	A. Wang

Environment:

	Kernel mode

Revision History:

	05/19/97		awang		Initial of Toshiba ATM 155 Device Driver.

--*/

#include "precomp.h"
#pragma hdrstop

#define MODULE_NUMBER      MODULE_TBMETEOR



NDIS_STATUS
tbAtm155InitSRAM_1KVCs(
   IN  PADAPTER_BLOCK  pAdapter
   )
/*++

Routine Description:

   This routine will initialize SRAM which supports up to 1K VCs.

Arguments:

   pAdapter    -   Pointer to the ADAPTER_BLOCK that describes the NIC.

Return Value:

   NDIS_STATUS_SUCCESS     -   initialize SRAM successful
   NDIS_STATUS_FAILURE     -   failed to initialize SRAM

--*/
{
   NDIS_STATUS         Status = NDIS_STATUS_SUCCESS;
   PHARDWARE_INFO      pHwInfo = pAdapter->HardwareInfo;
   ULONG               pSRAM;
   USHORT              phData;
   PSRAM_1K_VC_MODE    pSramAddrTbl;


   DBGPRINT(DBG_COMP_INT, DBG_LEVEL_INFO,
       ("==>tbAtm155InitSRAM_1KVCs\n"));

   pSramAddrTbl = (PSRAM_1K_VC_MODE)pHwInfo->pSramAddrTbl;

   do
   {
       //
       // Zero SRAM first before setting up tables in SRAM.
       //
       for (pSRAM = pSramAddrTbl->pRx_AAL5_Big_Free_Slot;
            pSRAM < pSramAddrTbl->pEnd_Of_SRAM;
            pSRAM++)
       {
           TBATM155_PH_WRITE_SRAM(pAdapter, pSRAM, 0, &Status);
           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Clear SRAM failed! \n"));

               break;
           }
       }
       
       if (NDIS_STATUS_SUCCESS != Status)
       {
           break;
       }       

       //
       //  Initialize the Tx slot descriptors structure, containing 1K 4-word 
       //  entries for 1K VC, from 0xA000 to 0xAFFF in on-board SRAM.
       //  
       //  Write phData + 1, where phData is the VC of the entry.
       //
       for (pSRAM = pSramAddrTbl->pTx_Slot_Descriptors, phData = 1;
            pSRAM < pSramAddrTbl->pACR_LookUp_Tbl;
            pSRAM += SIZEOF_TX_SLOT_DESC, phData++)
       {
           TBATM155_PH_WRITE_SRAM(pAdapter, pSRAM, phData, &Status);
           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Initialize Tx Slot Descriptor in SRAM failed! \n"));
               break;
           }
       }
       
       if (NDIS_STATUS_SUCCESS != Status)
       {
           break;
       }       
       
       //
       //  Initialize the CBR schedule table #1 and CBR schedule table #2
       //  structure from 0xE000 to 0xFFFF in on-board SRAM.
       //  Each table contains 4K entries, and each entry is 1 word.
       //
       for (pSRAM = pSramAddrTbl->pCBR_Schedule_Tbl_1, 
            phData = CBR_SCHEDULE_ENTRY_EOT;
            pSRAM < pSramAddrTbl->pEnd_Of_SRAM;
            pSRAM += SIZEOF_CBR_SCHEDULE_ENTRY)
       {
           //
           // Initialize CBR schedule tables.
           //
           TBATM155_PH_WRITE_SRAM(pAdapter, pSRAM, phData, &Status);
           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Initialize CBR Schedule tables in SRAM failed! \n"));
               break;
           }
       }
       
       if (NDIS_STATUS_SUCCESS != Status)
       {
           break;
       }       
       
       
       //
       //  Initialize the ACR lookup table structure, containing 512 1-word 
       //  entries, from 0xB000 to 0xB1FF in on-board SRAM.
       //
       for (pSRAM = pSramAddrTbl->pACR_LookUp_Tbl, phData = 0;
            pSRAM < pSramAddrTbl->pReserved2;
            pSRAM += SIZEOF_ACR_LOOKUP_TBL, phData++)
       {
           TBATM155_PH_WRITE_SRAM(
                   pAdapter,
                   pSRAM, 
                   AcrLookUpTbl[phData], 
                   &Status);

           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Initialize CBR Schedule tables in SRAM failed! \n"));
               break;
           }
       }

   } while (FALSE);


   DBGPRINT(DBG_COMP_INT, DBG_LEVEL_INFO,
       ("<==tbAtm155InitSRAM_1KVCs\n"));

   return(Status);

}



NDIS_STATUS
tbAtm155InitSRAM_4KVCs(
   IN  PADAPTER_BLOCK  pAdapter
   )
/*++

Routine Description:

   This routine will initialize SRAM which supports up to 4K VCs.

Arguments:

   pAdapter    -   Pointer to the ADAPTER_BLOCK that describes the NIC.

Return Value:

   NDIS_STATUS_SUCCESS     -   initialize SRAM successful
   NDIS_STATUS_FAILURE     -   failed to initialize SRAM

--*/
{
   NDIS_STATUS         Status = NDIS_STATUS_SUCCESS;
   PHARDWARE_INFO      pHwInfo = pAdapter->HardwareInfo;
   ULONG               pSRAM;
   USHORT              phData;
   PSRAM_4K_VC_MODE     pSramAddrTbl;


   DBGPRINT(DBG_COMP_INT, DBG_LEVEL_INFO,
       ("==>tbAtm155InitSRAM_4KVCs\n"));

   pSramAddrTbl = (PSRAM_4K_VC_MODE)pHwInfo->pSramAddrTbl;

   do
   {
       //
       // Zero SRAM first before setting up tables in SRAM.
       //
       for (pSRAM = pSramAddrTbl->pRx_AAL5_Big_Free_Slot;
            pSRAM < pSramAddrTbl->pEnd_Of_SRAM;
            pSRAM++)
       {
           TBATM155_PH_WRITE_SRAM(pAdapter, pSRAM, 0, &Status);
           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Clear SRAM failed! \n"));

               break;
           }
       }
       
       if (NDIS_STATUS_SUCCESS != Status)
       {
           break;
       }       

       //
       //  Initialize the Tx slot descriptors structure, containing 1K 4-word 
       //  entries for 1K VC, from 0x28000 to 0x2C000 in on-board SRAM.
       //  
       //  Write phData + 1, where phData is the VC of the entry.
       //
       for (pSRAM = pSramAddrTbl->pTx_Slot_Descriptors, phData = 1;
            pSRAM < pSramAddrTbl->pABR_Schedule_Tbl;
            pSRAM += SIZEOF_TX_SLOT_DESC, phData++)
       {
           TBATM155_PH_WRITE_SRAM(pAdapter, pSRAM, phData, &Status);
           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Initialize Tx Slot Descriptor in SRAM failed! \n"));
               break;
           }
       }
       
       if (NDIS_STATUS_SUCCESS != Status)
       {
           break;
       }       
       
       //
       //  Initialize the CBR schedule table #1 and CBR schedule table #2
       //  structure from 0x2E000 to 0x30000 in on-board SRAM.
       //  Each table contains 4K entries, and each entry is 1 word.
       //
       for (pSRAM = pSramAddrTbl->pCBR_Schedule_Tbl_1, 
            phData = CBR_SCHEDULE_ENTRY_EOT;
            pSRAM < pSramAddrTbl->pRx_AAL5_B_Slot_Tags;
            pSRAM += SIZEOF_CBR_SCHEDULE_ENTRY)
       {
           //
           // Initialize CBR schedule tables.
           //
           TBATM155_PH_WRITE_SRAM(pAdapter, pSRAM, phData, &Status);
           if (NDIS_STATUS_SUCCESS != Status)
           {
               DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
                   ("Initialize CBR Schedule tables in SRAM failed! \n"));
               break;
           }
       }
       
       if (NDIS_STATUS_SUCCESS != Status)
       {
           break;
       }