📄 init.c
字号:
NdisGetPhysicalAddressLow(pRxReportQ->PhysicalAddress) + Offset);
//
// Init pHwInfo->PrevTxReportPa and pHwInfo->PrevRxReportPa
// to the beginning of Physical addresses of Tx/Rx report queues.
//
pHwInfo->PrevTxReportPa = NdisGetPhysicalAddressLow(pTxReportQ->TxReportQptrPa);
pHwInfo->PrevRxReportPa = NdisGetPhysicalAddressLow(pRxReportQ->RxReportQptrPa);
} while (FALSE);
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("<==tbAtm155AllocateReportQueues\n"));
return(Status);
}
VOID
tbAtm155SetBufSizesOfCtrl2Reg(
IN PADAPTER_BLOCK pAdapter,
OUT PTB155PCISAR_CNTRL2 pRegControl2
)
/*++
Routine Description:
This routine will get buffer sizes for Control 2 regiter of Meteor
based on the buffer sizes set in registrys.
Arguments:
pAdapter - Pointer to the ADAPTER_BLOCK that describes the nic.
pRegControl2 - Pointer to the Control2 of Meteor SAR registers
Return Value:
--*/
{
PTBATM155_REGISTRY_PARAMETER pRegistryParameter = pAdapter->RegistryParameters;
ULONG tmp;
//
// Get Small buffer sizes first.
//
tmp = pRegistryParameter[TbAtm155SmallReceiveBufferSize].Value / sizeof(ULONG);
if (tmp < TBATM155_CTRL2_MIN_SMALL_BSIZE)
{
tmp = TBATM155_CTRL2_MIN_SMALL_BSIZE;
}
else if (tmp > TBATM155_CTRL2_MAX_SMALL_BSIZE)
{
tmp = TBATM155_CTRL2_MAX_SMALL_BSIZE;
}
if (tmp == TBATM155_CTRL2_MAX_SMALL_BSIZE)
{
//
// According to spec. 512lw is specified by programming
// this field with value 0.
//
tmp = 0;
}
(*pRegControl2).Small_Slot_Size = tmp;
//
// Get Big buffer sizes now.
//
tmp = pRegistryParameter[TbAtm155BigReceiveBufferSize].Value;
if ((tmp > 0) && (tmp <= BLOCK_1K))
{
tmp = 0;
}
else if ((tmp > BLOCK_1K) && (tmp <= BLOCK_2K))
{
tmp = 1;
}
else if ((tmp > BLOCK_2K) && (tmp <= BLOCK_4K))
{
tmp = 2;
}
else if ((tmp > BLOCK_4K) && (tmp <= BLOCK_8K))
{
tmp = 3;
}
else if ((tmp > BLOCK_8K) && (tmp <= BLOCK_10K))
{
tmp = 4;
}
else if ((tmp > BLOCK_10K) && (tmp <= BLOCK_16K))
{
tmp = 5;
}
else
{
tmp = 5;
}
(*pRegControl2).Big_Slot_Size = tmp;
}
NDIS_STATUS
tbAtm155InitRegisters(
IN PADAPTER_BLOCK pAdapter
)
/*++
Routine Description:
This routine will initialize
1. receive & transmit report queues.
2. the CSR registers on the NIC.
Arguments:
pAdapter - Pointer to the ADAPTER_BLOCK that describes the nic.
Return Value:
NDIS_STATUS_SUCCESS - initialize registers successfully.
NDIS_STATUS_FAILURE - failed to initialize the registers.
--*/
{
PHARDWARE_INFO pHwInfo = pAdapter->HardwareInfo;
PRX_REPORT_QUEUE pRxReportQ = &pAdapter->RxReportQueue;
PTX_REPORT_QUEUE pTxReportQ = &pAdapter->TxReportQueue;
PRX_REPORT_QUEUE_ENTRY Offset_Rx;
PTX_REPORT_QUEUE_ENTRY Offset_Tx;
TB155PCISAR_CNTRL1 regControl1, regControl1_set;
TB155PCISAR_CNTRL2 regControl2;
TX_FS_LIST_PTRS regTxFsListPtrs;
TX_ABR_NRM_TRM regCTxAbrNrmTrm;
INTR_ENB_REGISTER regIntr;
NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
UINT i;
INTR_HLDOFF_REG regIntrHldoff;
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("==>tbAtm155InitRegisters\n"));
//
// Let's initialize SRAM.
//
if (pHwInfo->fAdapterHw & TBATM155_METEOR_4KVC)
{
Status = tbAtm155InitSRAM_4KVCs(pAdapter);
}
else
{
Status = tbAtm155InitSRAM_1KVCs(pAdapter);
}
if (NDIS_STATUS_SUCCESS != Status)
{
DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
("tbAtm155InitSRAM failed! Status: 0x%x\n", Status));
return(Status);
}
//
// Soft reset the NIC one more time here.
//
tbAtm155SoftresetNIC(pHwInfo);
//
// Program the 155 PCI SAR Control1 register.
//
regControl1.reg = 0;
regControl1.Phy_Cell_Mode_Enb = 1;
//
// If we are in the middle of the reset, don't start transmitter
// and receiver now.
//
if (!ADAPTER_TEST_FLAG(pAdapter, fADAPTER_RESET_IN_PROGRESS))
{
regControl1.Rx_Enb = 1;
regControl1.Tx_Enb = 1;
}
if (pHwInfo->fAdapterHw & TBATM155_METEOR_4KVC)
{
regControl1.VC_Mode_Sel = 3; // 4K VCs supported.
regControl1.PCI_MRM_Sel = 1;
}
else
{
regControl1.VC_Mode_Sel = 1; // 1K VCs supported.
}
regControl1_set = regControl1;
/* Clear Phy_IF_Reset & Set Cell_mode */
regControl1.reg = (regControl1_set.reg & 0xfffffc00) | 0x080;;
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->SAR_Cntrl1,
regControl1.reg);
//
// Initialize PHY Controller based on the detection
//
if (pHwInfo->fAdapterHw & TBATM155_PHY_SUNI_LITE)
{
Status = tbAtm155InitSuniLitePhyRegisters(pAdapter);
}
else
{
Status = tbAtm155InitPLC2PhyRegisters(pAdapter);
}
if (!ADAPTER_TEST_FLAG(pAdapter, fADAPTER_RESET_IN_PROGRESS))
{
//
// Initialize other common variables.
//
pHwInfo->CellClockRate = TBATM155_CELL_CLOCK_RATE;
pAdapter->MaximumBandwidth = ATM_155 / CELL_SIZE;
pAdapter->MinimumCbrBandwidth = TBATM155_MIN_CBR_BANDWIDTH;
pAdapter->MinimumAbrBandwidth = TBATM155_MIN_ABR_BANDWIDTH;
#if AW_QOS
//
// The Number of available CBR VCs
// 9/17/97 - Please read the note where declares this
// variable (in SW.H).
//
pAdapter->NumOfAvailableCbrVc = MAX_SUPPORTED_CBR_VC;
#endif // end of AW_QOS
pAdapter->NumOfAvailVc_B = (pHwInfo->SarInfo->MaxRecvBufferCount / 3);
// pAdapter->NumOfAvailVc_B = pHwInfo->SarInfo->MaxRecvBufferCount;
pAdapter->NumOfAvailVc_S = pAdapter->NumOfAvailVc_B;
}
pAdapter->RemainingTransmitBandwidth = pAdapter->MaximumBandwidth;
if (NDIS_STATUS_SUCCESS != Status)
{
DBGPRINT(DBG_COMP_RESET, DBG_LEVEL_ERR,
("Failed to initialize the PHY registers\n"));
}
//
// 1. initialize Transmit report queue.
// 2. initialize Tx_Report_Ptr register also.
//
NdisZeroMemory (
(PVOID)(pTxReportQ->VirtualAddress),
(ULONG)(pTxReportQ->Size));
for (Offset_Tx = pTxReportQ->TxReportQptrVa, i = 0;
i <= pHwInfo->MaxIdxOfTxReportQ;
Offset_Tx++, i++)
{
Offset_Tx->TxReportQDWord.Own = 1; // set owned by 155 PCI SAR
}
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Tx_Report_Base,
NdisGetPhysicalAddressLow(pTxReportQ->TxReportQptrPa));
//
// 1. initialize Receive report queue.
// 2. initialize Rx_Report_Ptr register.
//
NdisZeroMemory (
(PVOID)(pRxReportQ->VirtualAddress),
(ULONG)(pRxReportQ->Size));
for (Offset_Rx = pRxReportQ->RxReportQptrVa, i = 0;
i <= pHwInfo->MaxIdxOfRxReportQ;
Offset_Rx++, i++)
{
Offset_Rx->RxReportQDWord0.Own = 1; // set owned by 155 PCI SAR
}
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Rx_Report_Base,
NdisGetPhysicalAddressLow(pRxReportQ->RxReportQptrPa));
//
// Program the 155 PCI SAR Control2 register.
//
regControl2.reg = 0;
tbAtm155SetBufSizesOfCtrl2Reg(pAdapter, ®Control2);
//
// Set Reassembly timeout time.
//
regControl2.Rx_RATO_Time = 15; // Range is 2-15.
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->SAR_Cntrl2,
regControl2.reg);
//
// Program the Tx_ABR_Nrm_Trm register which is used to store
// 2 sets of Nrm & Trm values for each of the 2 ABR parameter base
// sets supported by 155 PCI SAR.
// This register should be written at initialization time only.
// Line Rate = 353,208 cells/s
// Nrm (Base 1 & 2) = 32
// Trm (Base 1 & 2) = 100 ms
//
regCTxAbrNrmTrm.reg = 0;
regCTxAbrNrmTrm.Line_Rate_Exp = 0x12;
//=================================
#if ABR_CODE
//=================================
regCTxAbrNrmTrm.Trm_1 = TBATM155_TRM_100MS;
regCTxAbrNrmTrm.Nrm_1 = TBATM155_NRM_32CELLS;
regCTxAbrNrmTrm.Trm_2 = TBATM155_TRM_100MS;
regCTxAbrNrmTrm.Nrm_2 = TBATM155_NRM_32CELLS;
//=================================
#endif // end of ABR_CODE
//=================================
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Tx_ABR_Nrm_Trm,
regCTxAbrNrmTrm.reg);
//=================================
#if ABR_CODE
//=================================
//
// Program the Tx_ABR_ADTF register which is used to store
// 2 sets of ADTF (ACR Decay Timer Factor) values.
// This register should be written at initialization time only.
//
// ADTF (Base 1 & 2) = 500 ms
//
regTxAbrADTF.reg = 0;
regTxAbrADTF.ADTF_1 = TBATM155_ADTF_500MS;
regTxAbrADTF.ADTF_2 = TBATM155_ADTF_500MS;
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Tx_ABR_ADTF,
regTxAbrADTF.reg);
//=================================
#endif // end of ABR_CODE
//=================================
//
// Hold Off the number of interrupts of TX/RX IOCs.
// Holdoff IOC count of TX/RX = 10
// Holdoff IOC time of TX/RX = 24ms
//
regIntrHldoff.reg = 0;
regIntrHldoff.Rx_IOC_Hldoff_Wr = 1;
regIntrHldoff.Tx_IOC_Hldoff_Wr = 1;
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Intr_Hldoff,
regIntrHldoff.reg);
regIntrHldoff.Rx_IOC_Hldoff_Cnt = RX_IOC_HLDOFF_CNT;
regIntrHldoff.Rx_IOC_Hldoff_Time = RX_IOC_HLDOFF_TIME;
regIntrHldoff.Tx_IOC_Hldoff_Cnt = TX_IOC_HLDOFF_CNT;
regIntrHldoff.Tx_IOC_Hldoff_Time = TX_IOC_HLDOFF_TIME;
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Intr_Hldoff,
regIntrHldoff.reg);
regIntrHldoff.Rx_IOC_Hldoff_Wr = 0;
regIntrHldoff.Tx_IOC_Hldoff_Wr = 0;
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Intr_Hldoff,
regIntrHldoff.reg);
//
// Program the 155 PCI SAR Control1 register.
//
regTxFsListPtrs.reg = 0;
regTxFsListPtrs.Tx_FS_List_Valid = 1;
regTxFsListPtrs.Tx_FS_List_Tail = pHwInfo->MaxIdxOfTxReportQ;
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Tx_FS_List_ptrs,
regTxFsListPtrs.reg);
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->SAR_Cntrl1,
regControl1_set.reg);
//
// Clear Interrupt Status register first
//
TBATM155_READ_PORT(
&pHwInfo->TbAtm155_SAR->Intr_Status,
®Intr.reg);
TBATM155_WRITE_PORT(
&pHwInfo->TbAtm155_SAR->Intr_Status,
regIntr.reg);
//
// Set Interrupt Enable register but enable later.
//
pHwInfo->InterruptMask = TBATM155_REG_INT_VALID;
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("<==tbAtm155InitRegisters\n"));
return(Status);
}
VOID
tbAtm155InitSarParameters(
IN PADAPTER_BLOCK pAdapter
)
/*++
Routine Description:
This routine will initialize the SAR data parameters.
Arguments:
pAdapter - Pointer to the adapter block.
Return Value:
--*/
{
PHARDWARE_INFO pHwInfo = pAdapter->HardwareInfo;
PSAR_INFO pSar = pHwInfo->SarInfo;
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("==>tbAtm155InitSarParameters\n"));
//
// Initialize the variables of keeping track of Tx & Rx slots.
//
pSar->XmitDmaQ.MaximumTransmitSlots = pHwInfo->NumOfVCs;
pSar->RecvDmaQ.MaximumReceiveBigSlots = pHwInfo->NumOfVCs;
pSar->RecvDmaQ.MaximumReceiveSmallSlots = pHwInfo->NumOfVCs;
pSar->XmitDmaQ.RemainingTransmitSlots = pHwInfo->NumOfVCs;
pSar->XmitDmaQ.PrevTxReportQIndex = 0;
#if DBG
pSar->XmitDmaQ.dbgTotalPostedTxSlots = 0;
#endif // end of DBG
pSar->RecvDmaQ.RemainingReceiveBigSlots = pHwInfo->NumOfVCs;
pSar->RecvDmaQ.RemainingReceiveSmallSlots = pHwInfo->NumOfVCs;
pSar->RecvDmaQ.CurrentSlotTagOfBigBufQ = 1;
pSar->RecvDmaQ.CurrentSlotTagOfSmallBufQ = 1;
pSar->RecvDmaQ.PrevRxReportQIndex = 0;
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("<==tbAtm155InitSarParameters\n"));
}
NDIS_STATUS
tbAtm155InitSarSegment(
IN PADAPTER_BLOCK pAdapter
)
/*++
Routine Description:
This routine will initialize the SAR data structure and the drivers state
information for the SAR segment.
Arguments:
pAdapter - Pointer to the adapter block.
Return Value:
NDIS_STATUS_SUCCESS if we have successfully initialzied the SAR.
NDIS_STATUS_RESOURCES if we are unable to allocate necessary resources.
--*/
{
NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
PSAR_INFO pSar;
PHARDWARE_INFO pHwInfo = pAdapter->HardwareInfo;
PTBATM155_REGISTRY_PARAMETER pRegistryParameter;
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
("==>tbAtm155InitSarSegment\n"));
do
{
//
// Allocate memory for the sar.
//
ALLOCATE_MEMORY(&Status, &pSar, sizeof(SAR_INFO), '20DA');
if (NDIS_STATUS_SUCCESS != Status)
{
DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -