init.c

网络驱动开发

               ("Unable to read the CommandWord\n"));

           return(NDIS_STATUS_FAILURE);
       }

       if (((CommandWord & PCI_ENABLE_IO_SPACE) != PCI_ENABLE_IO_SPACE) ||
           ((CommandWord & PCI_ENABLE_MEMORY_SPACE) != PCI_ENABLE_MEMORY_SPACE) ||
           ((CommandWord & PCI_ENABLE_BUS_MASTER) != PCI_ENABLE_BUS_MASTER))
       {
           DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
               ("Invalid command word: 0x%x\n", CommandWord));

           return(NDIS_STATUS_FAILURE);
       }

       DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
           ("Successfully wrote command word: 0x%x\n", CommandWord));
   }

   //
   //	For noisy debug dump what we find in the PCI space.
   //
   dbgDumpPciCommonConfig(pAdapter);

   DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
       ("<==tbAtm155ReadPciConfiguration\n"));

   return(NDIS_STATUS_SUCCESS);

}


VOID
tbAtm155SoftresetNIC(
   IN  PHARDWARE_INFO  pHwInfo
   )
/*++

Routine Description:

   This routine issues a soft reset to the NIC.

Arguments:

   pHwInfo     -   Pointer to the HARDWARE_INFORMATION block that describes the nic.

Return Value:

--*/
{
   TB155PCISAR_CNTRL2      regControl2;

   DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
       ("==>tbAtm155SoftresetNIC(\n"));


   TBATM155_READ_PORT(
       &pHwInfo->TbAtm155_SAR->SAR_Cntrl2,
       &regControl2.reg);

   regControl2.Soft_Reset = 1;     // set the soft reset bit

   TBATM155_WRITE_PORT(
       &pHwInfo->TbAtm155_SAR->SAR_Cntrl2,
       regControl2.reg);

   NdisStallExecution(1);          // let's give a 1-ms-delay.

   TBATM155_READ_PORT(
       &pHwInfo->TbAtm155_SAR->SAR_Cntrl2,
       &regControl2.reg);

   if (regControl2.Soft_Reset != 1)
   {
       DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
           ("Soft_reset bit is not set\n"));
   }

   regControl2.Soft_Reset = 0;     // we need to clear the bit.

   TBATM155_WRITE_PORT(
       &pHwInfo->TbAtm155_SAR->SAR_Cntrl2,
       regControl2.reg);

   TBATM155_READ_PORT(
       &pHwInfo->TbAtm155_SAR->SAR_Cntrl2,
       &regControl2.reg);

   if (regControl2.Soft_Reset != 0)
   {
       DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
           ("Soft_reset bit is not cleared\n"));
   }

   DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
       ("<==tbAtm155SoftresetNIC(\n"));

}


NDIS_STATUS
tbAtm155GetHardwareInformation(
   IN	PADAPTER_BLOCK	pAdapter
   )
/*++

Routine Description:

   This routine will set the hardware information including reading
   in the manufacturer address for NIC and setting the
   offsets for the other information that will be needed.

Arguments:

   pAdapter	-	Pointer to the adapter block to save the information.

Return Value:

   NDIS_STATUS_SUCCESS     if everything went ok.
   NDIS_STATUS_FAILURE     otherwise.

--*/
{
   NDIS_STATUS             Status;
   PHARDWARE_INFO          pHwInfo;
   UINT                    c;
   BOOLEAN                 fCopyNetworkAddress = TRUE;


   DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
       ("==>tbAtm155GetHardwareInformation\n"));


   do
   {
       //
       //	Initialize the hardware info.
       //
       pHwInfo = pAdapter->HardwareInfo;

       //
       //	Map the chunk of memory that was given to us.
       //
       Status = NdisMMapIoSpace(
                   &pHwInfo->VirtualIoSpace,
                   pAdapter->MiniportAdapterHandle,
                   pHwInfo->PhysicalIoSpace,
                   pHwInfo->IoSpaceLength);
       if (NDIS_STATUS_SUCCESS != Status)
       {
           DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
               ("Unable to map needed memory space\n"));

           break;
       }

       //
       //	Set SAR offset
       //  (if use this VirtualIoSpace, the function NdisReadRegisterUlong
       //   will be used).
       //
       pHwInfo->TbAtm155_SAR = (PTBATM155_SAR)(pHwInfo->VirtualIoSpace);

       //
       //	Set PHY offset
       //
       pHwInfo->Phy = (ULONG)PHY_DEVICE_OFFSET;

       // 
       // Must soft reset the NIC before access serial EEPROM & PHY regiters
       // 
       tbAtm155SoftresetNIC(pHwInfo);

       //
       //	Read in the manufacturer address for the nic.
       //
       Status = tbAtm155Read_PermanentAddress(
                   pAdapter,
                   pHwInfo->PermanentAddress);

       if (NDIS_STATUS_SUCCESS != Status)
       {
           DBGPRINT(DBG_COMP_INIT,DBG_LEVEL_ERR,
               ("Read Node address failed! Status: 0x%x\n", Status));
           break;
       }

       for (fCopyNetworkAddress = TRUE, c = 0; c < ATM_MAC_ADDRESS_LENGTH; c++)
       {
           if (pHwInfo->StationAddress[c] != 0x0ff)
           {
               fCopyNetworkAddress = FALSE;
               break;
           }
       }


       if (fCopyNetworkAddress == TRUE)
       {
           //
           //	Save the permanent address in the station address by default.
           //
           NdisMoveMemory(
               pHwInfo->StationAddress,
               pHwInfo->PermanentAddress,
               ATM_MAC_ADDRESS_LENGTH);
       }

       dbgDumpHardwareInformation(pHwInfo);

   } while (FALSE);
   
   DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
       ("<==tbAtm155GetHardwareInformation\n"));

   return(Status);
}

VOID
tbAtm155FreeResources(
   IN PADAPTER_BLOCK pAdapter
   )
/*++

Routine Description:

   This routine will free the resources that were allocated for an adapter.

Arguments:

   pAdapter    -   Pointer to the adapter block whose resources we need to
                   free.

Return Value:

--*/
{
   PHARDWARE_INFO      pHwInfo;
   PSAR_INFO           pSar;
   PTX_REPORT_QUEUE    pTxReportQ;    
   PRX_REPORT_QUEUE    pRxReportQ;    


   DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
       ("==>tbAtm155FreeResources\n"));

   if (NULL != pAdapter)
   {
       if (NULL != pAdapter->RegistryParameters)
       {

           FREE_MEMORY(
               pAdapter->RegistryParameters,
               sizeof(TBATM155_REGISTRY_PARAMETER) * TbAtm155MaxRegistryEntry);
       }

       if (NULL != pAdapter->HardwareInfo)
       {
           pHwInfo = pAdapter->HardwareInfo;

           if (HW_TEST_FLAG(pHwInfo, fHARDWARE_INFO_INTERRUPT_REGISTERED))
           {
               NdisMDeregisterInterrupt(&pHwInfo->Interrupt);
           }

           if (NULL != pHwInfo->SarInfo)
           {
               pSar = pHwInfo->SarInfo;

               //
               //	Free up the transmit and receive DMA resources
               //
               tbAtm155FreeReceiveBufferQueue(pAdapter, &pSar->RecvDmaQ.CompletingSmallBufQ);
               tbAtm155FreeReceiveBufferQueue(pAdapter, &pSar->RecvDmaQ.CompletingBigBufQ);

               tbAtm155FreeReceiveBufferQueue(pAdapter, &pSar->FreeSmallBufferQ);
               tbAtm155FreeReceiveBufferQueue(pAdapter, &pSar->FreeBigBufferQ);

               NdisFreeSpinLock(&pSar->RecvDmaQ.lock);


               tbAtm155FreePacketQueue(&pSar->XmitDmaQ.DmaWait);

               NdisFreeSpinLock(&pSar->XmitDmaQ.lock);

               //
               //	Free the spin lock used to protect the free list of
               //	transmit segments.
               //
               NdisFreeSpinLock(&pSar->lockFreeXmitSegment);

               //
               //	Free up the memory.
               //
               FREE_MEMORY(pSar, sizeof(SAR_INFO));
           }

           if (NULL != pHwInfo->PortOffset)
           {
               NdisMDeregisterIoPortRange(
                   pAdapter->MiniportAdapterHandle,
                   pHwInfo->InitialPort,
                   pHwInfo->NumberOfPorts,
                   pHwInfo->PortOffset);
           }
		
           if (NULL != pHwInfo->VirtualIoSpace)
           {
               NdisMUnmapIoSpace(
                   pAdapter->MiniportAdapterHandle,
                   pHwInfo->VirtualIoSpace,
                   pHwInfo->IoSpaceLength);
           }
		
           if (NULL != pHwInfo->pSramAddrTbl)
           {
               if (pHwInfo->fAdapterHw & TBATM155_METEOR_4KVC)
               {
                   FREE_MEMORY(
                       pHwInfo->pSramAddrTbl, 
                       sizeof(SRAM_4K_VC_MODE));
               }
               else
               {
                   FREE_MEMORY(
                       pHwInfo->pSramAddrTbl, 
                       sizeof(SRAM_1K_VC_MODE));
               }
           }

           //
           //	Free the spin lock for the hardware information.
           //
           NdisFreeSpinLock(&pHwInfo->Lock);

           //
           //	Free the memory used for the hardware information.
           //
           FREE_MEMORY(pHwInfo, sizeof(HARDWARE_INFO));
       }

       pRxReportQ = &pAdapter->RxReportQueue;

       if (NULL != pRxReportQ->VirtualAddress)
       {
           //
           // free up the receive report queue.
           //
           NdisMFreeSharedMemory(
               pAdapter->MiniportAdapterHandle,
               pRxReportQ->Size,
               FALSE,
               pRxReportQ->VirtualAddress,
               pRxReportQ->PhysicalAddress);
       }

       pTxReportQ = &pAdapter->TxReportQueue;

       if (NULL != pTxReportQ->VirtualAddress)
       {
           //
           // free up the transmit report queue.
           //
           NdisMFreeSharedMemory(
               pAdapter->MiniportAdapterHandle,
               pTxReportQ->Size,
               FALSE,
               pTxReportQ->VirtualAddress,
               pTxReportQ->PhysicalAddress);

       }

       dbgFreeDebugInformation(pAdapter->DebugInfo);

       ASSERT(IsListEmpty(&pAdapter->ActiveVcList));
       ASSERT(IsListEmpty(&pAdapter->InactiveVcList));

       //
       //	Free up the spin lock for the adapter block.
       //
       NdisFreeSpinLock(&pAdapter->lock);
       NdisFreeSpinLock(&pAdapter->VcHashLock);

       //
       //	Free the memory allocated for the adapter block.
       //
       FREE_MEMORY(pAdapter, sizeof(ADAPTER_BLOCK));

   }

   DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
       ("<==tbAtm155FreeResources\n"));
}


NDIS_STATUS
tbAtm155AllocateReportQueues(
   IN  PADAPTER_BLOCK  pAdapter
	)
/*++

Routine Description:

   This routine will allocate receive & transmit report queues.

Arguments:

   pAdapter    -   Pointer to the ADAPTER_BLOCK that describes the nic.

Return Value:

   NDIS_STATUS_SUCCESS     - if allocate report queues OK.
   NDIS_STATUS_RESOURCES   - if allocate report queues failed.

--*/
{
   PHARDWARE_INFO      pHwInfo = pAdapter->HardwareInfo;
   NDIS_STATUS         Status = NDIS_STATUS_SUCCESS;
   PRX_REPORT_QUEUE    pRxReportQ = &pAdapter->RxReportQueue;
   PTX_REPORT_QUEUE    pTxReportQ = &pAdapter->TxReportQueue;
   ULONG               Offset;
   ULONG               DmaAlignmentRequired;
   PUCHAR              StartVa;


	DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
		("==>tbAtm155AllocateReportQueues\n"));


   do {

       //
       // Allocate a Transmit report queue
	    //
	    //	- Get the DMA alignment that we need.
	    //

#if (WINVER < 0x0501)
       DmaAlignmentRequired = NdisGetCacheFillSize();
#else
       DmaAlignmentRequired = gDmaAlignmentRequired;
#endif
       if (DmaAlignmentRequired < TBATM155_MIN_QUEUE_ALIGNMENT)
	    {
		    DmaAlignmentRequired = TBATM155_MIN_QUEUE_ALIGNMENT;
	    }

       //
       //  - Calculate the total size of the Tx queue.
       //
       pTxReportQ->Size = 
           ((sizeof(TX_REPORT_QUEUE_ENTRY) * (pHwInfo->MaxIdxOfTxReportQ+1))
            + DmaAlignmentRequired);

       DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
           ("pTxReportQ->Size = 0x%lx, size of TX_REPORT_QUEUE_ENTRY (%d)\n",
            pTxReportQ->Size, sizeof(TX_REPORT_QUEUE_ENTRY)));

       NdisMAllocateSharedMemory(
           pAdapter->MiniportAdapterHandle,
           pTxReportQ->Size,
           FALSE,
           &pTxReportQ->VirtualAddress,
           &pTxReportQ->PhysicalAddress);

	    if ((NULL == pTxReportQ->VirtualAddress) ||
			 (0 != pTxReportQ->PhysicalAddress.HighPart))
       {
           DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
               ("Unable to allocate the tx report queue\n"));
           Status = NDIS_STATUS_RESOURCES;
           break;
       }

       //
       //  - Set the aligned Virtual address and Physical address.
       //
       Offset  = DmaAlignmentRequired -
                   (ULONG)((ULONG_PTR)pTxReportQ->VirtualAddress % DmaAlignmentRequired);
       StartVa = ((PUCHAR)pTxReportQ->VirtualAddress + Offset);
       pTxReportQ->TxReportQptrVa = (PTX_REPORT_QUEUE_ENTRY)StartVa;

       NdisSetPhysicalAddressLow(
           pTxReportQ->TxReportQptrPa,
           NdisGetPhysicalAddressLow(pTxReportQ->PhysicalAddress) + Offset);

       //
       //  - Calculate the total size of the Rx queue.
       //
       pRxReportQ->Size = 
           ((sizeof(RX_REPORT_QUEUE_ENTRY) * (pHwInfo->MaxIdxOfRxReportQ+1))
            + DmaAlignmentRequired);

       DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_INFO,
           ("pRxReportQ->Size = 0x%ld, size of RX_REPORT_QUEUE_ENTRY (%d)\n",
            pRxReportQ->Size, sizeof(RX_REPORT_QUEUE_ENTRY)));

       NdisMAllocateSharedMemory(
           pAdapter->MiniportAdapterHandle,
           pRxReportQ->Size,
           FALSE,
           &pRxReportQ->VirtualAddress,
           &pRxReportQ->PhysicalAddress);

       if ((NULL == pRxReportQ->VirtualAddress) ||
			 (0 != pRxReportQ->PhysicalAddress.HighPart))
       {
           DBGPRINT(DBG_COMP_INIT, DBG_LEVEL_ERR,
               ("Unable to allocate the rx report queue\n"));
           Status = NDIS_STATUS_RESOURCES;
           break;
       }

       //
       //  - Set the aligned Virtual address and Physical address.
       //
   	Offset  = DmaAlignmentRequired -
				  (ULONG)((ULONG_PTR)pRxReportQ->VirtualAddress % DmaAlignmentRequired);
       StartVa = ((PUCHAR)pRxReportQ->VirtualAddress + Offset);
       pRxReportQ->RxReportQptrVa = (PRX_REPORT_QUEUE_ENTRY)StartVa;

       NdisSetPhysicalAddressLow(
           pRxReportQ->RxReportQptrPa,