dedeclassemulator.pas

dede 的源代码 3.10b

        end;

   $12,{adc reg1, reg2}
   $13 {adc reg1, reg2}
      : case I1 of
          3 :  {adc reg2, reg1}  CL_Reg_to_Reg(Instruction)
          else {adc reg, memory} CL_Mod_Reg_RM(Instruction);
        end;
   $14,{adc reg8, imm_data}
   $15 {adc reg32, imm_data}
      : CL_Imm_to_A;

   $18,{sbb reg2, reg1}
   $19 {sbb reg2, reg1}
      : case I1 of
          3 :  {sbb reg2, reg1}  CL_Reg_to_Reg(Instruction);
        end;

   $1A,{sbb reg1, reg2}
   $1B {sbb reg1, reg2}
      : case I1 of
          3 :  {sbb reg2, reg1}  CL_Reg_to_Reg(Instruction)
          else {sbb reg, memory} CL_Mod_Reg_RM(Instruction);
        end;

   $1C,{sbb reg8, imm_data}
   $1D {sbb reg32, imm_data}
      : CL_Imm_to_A;

   $20,{and reg2, reg1}
   $21 {and reg2, reg1}
      : case I1 of
          3 :  {and reg2, reg1}  CL_Reg_to_Reg(Instruction);
        end;

   $22,{and reg1, reg2}
   $23 {and reg1, reg2}
      : case I1 of
          3 :  {and reg2, reg1}  CL_Reg_to_Reg(Instruction)
          else {and reg, memory} CL_Mod_Reg_RM(Instruction);
        end;
   $24,{and reg8, imm_data}
   $25 {and reg32, imm_data}
      : CL_Imm_to_A;

   $27: {daa} ClearRegister(rgEAX);

   $28,{sub reg2, reg1}
   $29 {sub reg2, reg1}
      : case I1 of
          3 :  {sub reg2, reg1}  CL_Reg_to_Reg(Instruction);
        end;

   $2A,{sub reg1, reg2}
   $2B {sub reg1, reg2}
      : case I1 of
          3 :  {sub reg2, reg1}  CL_Reg_to_Reg(Instruction)
          else {sub reg, memory} CL_Mod_Reg_RM(Instruction);
        end;

   $2C,{sub reg8, imm_data}
   $2D {sub reg32, imm_data}
      : CL_Imm_to_A;

   $2F: {das} ClearRegister(rgEAX);

   $30,{xor reg2, reg1}
   $31 {xor reg2, reg1}
      : case I1 of
          3 :  {xor reg2, reg1}  CL_Reg_to_Reg(Instruction);
        end;

   $32,{xor reg1, reg2}
   $33 {xor reg1, reg2}
      : case I1 of
          3 :  {xor reg2, reg1}  CL_Reg_to_Reg(Instruction)
          else {xor reg, memory} CL_Mod_Reg_RM(Instruction);
        end;

   $34,{sub reg8, imm_data}
   $35 {sub reg32, imm_data}
      : CL_Imm_to_A;

   $37: {aaa} ClearRegister(rgEAX);
   $3F: {aas} ClearRegister(rgEAX);

   $40..$47, {inc reg}
   $48..$4F  {dec reg}
      : begin
          DecodeOperandInfo(ORD(Instruction[1]),'11 111 reg', 1, _i1,_i2,_i3);
          ClearRegister(TRegister(_i3));
        end;

   $50..$57, {push reg}
   $58..$5F  {pop reg}
      : begin
          DecodeOperandInfo(ORD(Instruction[1]),'11 111 reg', 1, _i1,_i2,_i3);
          ClearRegister(TRegister(_i3));
        end;

   $66 {??}
      : if ORD(Instruction[2])=$BB {MOV BX, IMM_DATA}
        // Which is for the dynamic metods call DOI stuff
        then OffsInfReference(rgEAX, sOp);

   $69,{imul reg1, reg2, imm_data}
   $6B {imul reg, memory, imm_data}
      : ClearRegister(TRegister(i2));

   $80,
   $81,
   $82,
   $83
      : begin
          /////////////////////////////
          // "immediate to register" //
          /////////////////////////////
          DecodeOperandInfo(ORD(Instruction[2]),'11 111 reg', Min(ORD(Instruction[1]) mod 2,1), _i1,_i2,_i3);
          if _i1=3 {i1= 11} then
           begin
             {i2 = 000 -> add reg, imm_data}
             {i2 = 001 ->  or reg, imm_data}
             {i2 = 010 -> adc reg, imm_data}
             {i2 = 011 -> sbb reg, imm_data}
             {i2 = 100 -> and reg, imm_data}
             {i2 = 101 -> sub reg, imm_data}
             {i2 = 110 -> xor reg, imm_data}
             ClearRegister(TRegister(_i3));
           end;
        end;

   $86,
   $87  {xchg reg, memory}
      : if I1=3 then xchgRegister_Register(TRegister(I2),TRegister(I3))
                else ClearRegister(TRegister(I2));

   $88 {mov reg1, reg2}
      : ClearRegister(TRegister(i3));

   $89  {mov reg1, reg2}
      : case I1 of
          3 :  {mov reg1, reg2 }  movRegister_ptrRegister(TRegister(i3), TRegister(i2))
          else case ORD(Instruction[2]) of
            $45: {mov [ebp-xx], eax} movStackVar_Register(rgEAX,dGetStackVar(sOp));
            $4D: {mov [ebp-xx], ecx} movStackVar_Register(rgECX,dGetStackVar(sOp));
            $55: {mov [ebp-xx], edx} movStackVar_Register(rgEDX,dGetStackVar(sOp));
            $5D: {mov [ebp-xx], ebx} movStackVar_Register(rgEBX,dGetStackVar(sOp));
            $75: {mov [ebp-xx], esi} movStackVar_Register(rgESI,dGetStackVar(sOp));
            $7D: {mov [ebp-xx], edi} movStackVar_Register(rgEDI,dGetStackVar(sOp));
            $B8 : {mov eax, imm_data} movRegOffset(rgeax, sOp);
            $B9 : {mov ecx, imm_data} movRegOffset(rgecx, sOp);
            $BA : {mov edx, imm_data} movRegOffset(rgedx, sOp);
            $BB : {mov ebx, imm_data} movRegOffset(rgebx, sOp);
            $BC : {mov esp, imm_data} movRegOffset(rgesp, sOp);
            $BD : {mov ebp, imm_data} movRegOffset(rgebp, sOp);
            $BE : {mov esi, imm_data} movRegOffset(rgesi, sOp);
            $BF : {mov edi, imm_data} movRegOffset(rgedi, sOp)
            Else ClearRegister(TRegister(i3));
           end;
        end;

   $8A {mov reg2, reg1}
      : ClearRegister(TRegister(i2));

   $8B  {mov reg2, reg1}
      : case I1 of
          3 :  {mov reg2, reg1}  movRegister_ptrRegister(TRegister(i2), TRegister(i3))
          else case ORD(Instruction[2]) of
            $05: {mov eax, [offset]} movRegister_ptr(rgEAX, dGetOffset(sOp));
            $0D: {mov ecx, [offset]} movRegister_ptr(rgECX, dGetOffset(sOp));
            $15: {mov edx, [offset]} movRegister_ptr(rgEDX, dGetOffset(sOp));
            $1D: {mov ebx, [offset]} movRegister_ptr(rgEBX, dGetOffset(sOp));
            $35: {mov esi, [offset]} movRegister_ptr(rgESI, dGetOffset(sOp));
            $3D: {mov edi, [offset]} movRegister_ptr(rgEDI, dGetOffset(sOp));
            $45: {mov eax, [ebp-xx]} movRegister_StackVar(rgEAX,dGetStackVar(sOp));
            $4D: {mov ecx, [ebp-xx]} movRegister_StackVar(rgECX,dGetStackVar(sOp));
            $55: {mov edx, [ebp-xx]} movRegister_StackVar(rgEDX,dGetStackVar(sOp));
            $5D: {mov ebx, [ebp-xx]} movRegister_StackVar(rgEBX,dGetStackVar(sOp));
            $75: {mov esi, [ebp-xx]} movRegister_StackVar(rgESI,dGetStackVar(sOp));
            $7D: {mov edi, [ebp-xx]} movRegister_StackVar(rgEDI,dGetStackVar(sOp));
            Else
            // Only in casses like MOV REG, [EAX+EAX+Offs] -> REG should be cleared
            // All the other casses are for DOI MOV References
             case i3 of
                // Here we have only then MOV REG, [REG] case
                // MOV REG, [REG+Offs] is handled by DeDeDisAsm.ControlRef()
                0 : movRegister_ptrRegister(TRegister(i2), rgEAX);
                4 : ClearRegister(TRegister(i2));
                6 : OffsInfReference(TRegister(i3), sOp);
                7 : {mov REG, [REG1+n*REG2+Offset]}
                else ;
             end;
           end
        end;

   $8D {lea reg, memory}
      : ClearRegister(TRegister(i2));

   $8F
      : begin
          ////////////////
          // "register" //
          ////////////////
          DecodeOperandInfo(ORD(Instruction[2]),'11 111 reg', Min(ORD(Instruction[1]) mod 2,1), _i1,_i2,_i3);
          if _i1=3 {i1= 11} then
           begin
             {i2 = 000 ->  pop reg}
             ClearRegister(TRegister(_i3));
           end;
        end;

   $90..$97
      : begin
          DecodeOperandInfo(ORD(Instruction[1]),'11 111 reg', Min(ORD(Instruction[1]) mod 2,1), _i1,_i2,_i3);
          xchgRegister_Register(rgEAX, TRegister(_i3));
        end;

   $98: {cwd} ClearRegister(rgEAX);
   $99: {cwd} ClearRegister(rgEDX);
   $9F: {lahf} ClearRegister(rgEDX);

   $A0: {mov  al,  byte ptr [offset]} movRegister_ptr(rgEAX, dGetOffset(sOp));
   $A1: {mov eax, dword ptr [offset]} movRegister_ptr(rgEAX, dGetOffset(sOp));
   $A2: {mov  byte ptr [offset], al } movptr_Register(rgEAX, dGetOffset(sOp));
   $A3: {mov dword ptr [offset], eax} movptr_Register(rgEAX, dGetOffset(sOp));

   $B0..$B7 {mov reg, imm_data}
       : begin
           DecodeOperandInfo(ORD(Instruction[1]),'11 111 reg', 0, _i1,_i2,_i3);
           ClearRegister(TRegister(_i3));
         end;

   $B8..$BF {mov reg, imm_data}
       : begin
           DecodeOperandInfo(ORD(Instruction[1]),'11 111 reg', 1, _i1,_i2,_i3);
           movRegOffset(TRegister(_i3), sOp);
         end;

   $C0,
   $C1
      : begin
          DecodeOperandInfo(ORD(Instruction[2]),'11 111 reg', Min(ORD(Instruction[1]) mod 2,1), _i1,_i2,_i3);
            if _i1=3 {i1 = 11} then
            begin
              if _i2 in [0, {i2 = 000 -> rol reg, imm_data}
                         1, {i2 = 001 -> ror reg, imm_data}
                         2, {i2 = 010 -> rcl reg, imm_data}
                         3, {i2 = 011 -> rcr reg, imm_data}
                         4, {i2 = 100 -> shl reg, imm_data}
                         5, {i2 = 101 -> shl reg, imm_data}
                         7] {i2 = 111 -> sar reg, imm_data}
                 then ClearRegister(TRegister(_i3));
            end;
         end;

   $C6, {mov reg, imm_data}
   $C7  {mov reg, imm_data}
      : begin
          DecodeOperandInfo(ORD(Instruction[2]),'11 111 reg', ORD(Instruction[1]) mod 2, _i1,_i2,_i3);
          ClearRegister(TRegister(_i3));
        end;
   $D0,
   $D1
      : begin
          DecodeOperandInfo(ORD(Instruction[2]),'11 111 reg', Min(ORD(Instruction[1]) mod 2,1), _i1,_i2,_i3);
            if _i1=3 {i1 = 11} then
            begin
              if _i2 in [0, {i2 = 000 -> rol reg, 1}
                         1, {i2 = 001 -> ror reg, 1}
                         2, {i2 = 010 -> rcl reg, 1}
                         3, {i2 = 011 -> rcr reg, 1}
                         4, {i2 = 100 -> shl reg, 1}
                         5, {i2 = 101 -> shl reg, 1}
                         7] {i2 = 111 -> sar reg, 1}
                 then ClearRegister(TRegister(_i3));
            end;
         end;

   $D2,
   $D3
      : begin
          DecodeOperandInfo(ORD(Instruction[2]),'11 111 reg', Min(ORD(Instruction[1]) mod 2,1), _i1,_i2,_i3);
            if _i1=3 {i1 = 11} then
            begin
              if _i2 in [0, {i2 = 000 -> rol reg, cl}
                         1, {i2 = 001 -> ror reg, cl}
                         2, {i2 = 010 -> rcl reg, cl}
                         3, {i2 = 011 -> rcr reg, cl}
                         4, {i2 = 100 -> shl reg, cl}
                         5, {i2 = 101 -> shl reg, cl}
                         7] {i2 = 111 -> sar reg, cl}
                 then ClearRegister(TRegister(_i3));
            end;
         end;

   $D4: {aam} if Instruction[2]=#$0A then ClearRegister(rgEAX);
   $D5: {aad} if Instruction[2]=#$0A then ClearRegister(rgEAX);

   $F6,
   $F7
      : begin
          DecodeOperandInfo(ORD(Instruction[2]),'11 111 reg', Min(ORD(Instruction[1]) mod 2,1), _i1,_i2,_i3);
            if _i1=3 {i1 = 11} then
            begin
              if _i2 in [2, {i2 = 010 -> not reg}
                         3, {i2 = 011 -> neg reg}
                         4, {i2 = 100 -> mul reg}
                         5, {i2 = 101 -> imul reg}
                         6, {i2 = 110 -> div reg}
                         7] {i2 = 110 -> idiv reg}
                 then
                 if (ORD(Instruction[1]) mod 2) =0
                   then ClearRegister(rgEAX)
                   else begin
                     ClearRegister(rgEAX);
                     ClearRegister(rgEDX);
                   end;
            end
            else begin
              if _i2= 5 {i2 = 101 -> imul reg}
                 then ClearRegister(rgEAX);
            end;
        end;
   $FE,
   $FF
      : begin
          DecodeOperandInfo(ORD(Instruction[2]),'11 111 reg', ORD(Instruction[1]) mod 2, _i1,_i2,_i3);
            if _i1=3 {i1 = 11} then
              begin
                {i2 = 000 -> inc reg}
                {i2 = 001 -> dec reg}
                {i2 = 010 -> call reg}
                {i2 = 110 -> push reg}
                ClearRegister(TRegister(_i3));
              end;

            if (_i1 in [1,2] {i1 = 01, 10}) and (_i2=2 {i2 = 010}) and (ORD(Instruction[1])=$FF)
              Then begin
                // The DOI CALL [REG+Offs] references case
                OffsInfReference(TRegister(i3), sOp);
              end;
        end;
  End;


  ////////////////////////////////////////////////////////////////
  // Because of bad emulation 
  //
  // One of them is a call to procedure or function
  // In future return type could be saved in DSF file for the
  // functions that will change EAX apropritely
  ////////////////////////////////////////////////////////////////
  // This stuff has been removed because the emulator had been
  // improved a lot !!!
  ////////////////////////////////////////////////////////////////
  // Dec Time-To-Live
  //-------------------------------------------------------------------------------------
  // For RegIdx:=rgEAX to rgESP do Dec(ExpireCounter[RegIdx]);
  //
  // Check for expired values and clear them
  //-------------------------------------------------------------------------------------
  // For RegIdx:=rgEAX to rgESP do if ExpireCounter[RegIdx]<0 then ClearRegister(RegIdx);
  ///////////////////////////////////////////////////////////////////////////////////////
end;


initialization
  ESP:=TStringList.Create;
  Loc_Names:=TStringList.Create;
  Loc_StrVals:=TStringList.Create;
  dwESP:=TList.Create;
  Loc_Vars:=TList.Create;
  OffsInfArchive:=TOffsInfArchive.Create;

finalization
  ESP.Free;
  Loc_Names.Free;
  Loc_StrVals.Free;
  dwESP.Free;
  Loc_Vars.Free;
  OffsInfArchive.Free;

end.