rgbdata.vhd

i80时序说明

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RGBDATA is
port(
     RGBDATA: in  std_logic_vector(15 downto 0);
     LCDDATA: out std_logic_vector(15 downto 0);
         CLK: in  std_logic;
         RST: in  std_logic;
          RS: out std_logic;
          CS: out std_logic;
          WR: out std_logic;
          RD: out std_logic);
end;
architecture behav of RGBDATA is
signal LATCH_DATA:std_logic_vector(15 downto 0);
signal state:std_logic_vector(4 downto 0);
--state(3)=RS;state(2)=CS;state(1)=WR;state(0)=RD;
constant state0: std_logic_vector(4 downto 0) :="01111";--init select
constant state1: std_logic_vector(4 downto 0) :="01011";--chip select
constant state2: std_logic_vector(4 downto 0) :="01001";--wr is low
constant state3: std_logic_vector(4 downto 0) :="11011";--wr is high
begin
moore:process(RST,CLK)
      begin
      if RST='0' then
         state<=state0;
      elsif CLK='1' and CLK'event then
            case state is
                         when state0 => state<=state1;
                         when state1 => state<=state2;
                         when state2 => state<=state3;
                         when state3 => state<=state0;
                         when others => state<=state0;
            end case;
      end if; 
      end process;
mdata:process(state)
      begin
      if state=state1 then
         LATCH_DATA<=RGBDATA;
      end if;
      end process;
      LCDDATA<=LATCH_DATA;
           RS<=state(3);
           CS<=state(2);
           WR<=state(1);
           RD<=state(0);
end;