lan91c111_adapter.h

PXA255/270平台的 LAN91C111网卡驱动程序

/*
 *
 *    Copyright (c) Standard MicroSystems Corporation.  All Rights Reserved.
 *
 *				    LAN91C111 Driver for Windows CE .NET
 *
 *							 Revision History
 *_______________________________________________________________________________
 *     Author		  Date		Version		Description
 *_______________________________________________________________________________
 * Pramod Bhardwaj  6/18/2002	  0.1		Beta Release
 *					7/15/2002	  1.0       Release 
 *					1/22/2003     1.1		Removed some platform dependencies
 *					3/27/2003     1.2       Used alloc interrupt
 * TScho			2/15/2004	  1.2.0		Performance changes (Beta)
 * TScho			2/20/2004	  1.2.1		Multi-packet indication (Beta)
 * TScho			2/25/2004	  1.2.2		Multicast fixed (Beta)
 * TScho			2/26/2004	  2.1		Release for CE 5.0
 *_______________________________________________________________________________
 *
 *Description
 *              Hardware specific and driver datastructure declarations
 *
 */
#ifndef __LAN91C111_ADAPTER__
#define __LAN91C111_ADAPTER__


//NDIS Version Declaration
#ifdef NDIS51_MINIPORT
#define DRIVER_NDIS_MAJOR_VERSION 5
#else
#define DRIVER_NDIS_MAJOR_VERSION 4
#endif
#define DRIVER_NDIS_MINOR_VERSION 0
#define DRIVER_NDIS_VERSION ((DRIVER_NDIS_MAJOR_VERSION << 8) + DRIVER_NDIS_MINOR_VERSION)

#define DRIVER_BUILD_NUM 260204


#define PrintDebugMsg	RETAILMSG //DEBUGMSG

//Windows CE debug zones
#define ZONEID_INIT			0
#define ZONEID_INTR			1
#define ZONEID_TX			2
#define ZONEID_RX			3
#define ZONEID_RX_OVRN		4
#define ZONEID_MC			5
//...
#define ZONEID_WARN			14
#define ZONEID_ERROR		15

#define ZONEMASK_INIT		(1<<ZONEID_INIT)
#define ZONEMASK_INTR		(1<<ZONEID_INTR)
#define ZONEMASK_TX			(1<<ZONEID_TX)
#define ZONEMASK_RX			(1<<ZONEID_RX)
#define ZONEMASK_RX_OVRN	(1<<ZONEID_RX_OVRN)
#define ZONEMASK_MC			(1<<ZONEID_MC)
//...
#define ZONEMASK_WARN		(1<<ZONEID_WARN)
#define ZONEMASK_ERROR		(1<<ZONEID_ERROR)

#ifdef DEBUG
// These macros are used as the first arg to DEBUGMSG.
#define ZONE_INIT			DEBUGZONE(ZONEID_INIT)
#define ZONE_INTR			DEBUGZONE(ZONEID_INTR)
#define ZONE_TX				DEBUGZONE(ZONEID_TX)
#define ZONE_RX				DEBUGZONE(ZONEID_RX)
#define ZONE_RX_OVRN		DEBUGZONE(ZONEID_RX_OVRN)
#define ZONE_MC				DEBUGZONE(ZONEID_MC)
//...
#define ZONE_WARN			DEBUGZONE(ZONEID_WARN)
#define ZONE_ERROR			DEBUGZONE(ZONEID_ERROR)
#else
// For release configurations, these conditionals are always 0.
#define ZONE_INIT		1
#define ZONE_INTR		1
#define ZONE_TX			1
#define ZONE_RX			1
#define ZONE_RX_OVRN	1
#define ZONE_MC			1
//...
#define ZONE_WARN		1
#define ZONE_ERROR		1
#endif


//---------------MINIPORT PACKET RELATED--------------------------
//The MINIPORT Packet structure.  One per active send request.
typedef struct _MINIPORT_PACKET
{
	struct _MINIPORT_PACKET	*Next;			//Next packet on queue.
	UCHAR					PacketNumber;	//Adapter Packet number.
	USHORT					PacketRange;
} MINIPORT_PACKET;
#define MINIPORT_PACKET_SIZE sizeof(MINIPORT_PACKET)

//The MINIPORT packet queue structur and macros
typedef struct _MINIPORT_PACKET_QUE
{
	MINIPORT_PACKET		*First;			//First packet on queue or 0
	MINIPORT_PACKET		*Last;			//Last packet on queue or &First
} MINIPORT_PACKET_QUE;
#define MAC_PACKET_QUE_SIZE sizeof(MAC_PACKET_QUE)

//Hardware packet representation.
typedef struct _SMC_PACK_HEADER
{
	USHORT	Status;
	USHORT	Range;
} SMC_PACK_HEADER;
#define SMC_PACK_HEADER_SIZE sizeof(SMC_PACK_HEADER)

//Clear packet queue macro.
#define ClearPacketQue(Que) {(Que).First = (MINIPORT_PACKET *) 0;                \
	(Que).Last  = (MINIPORT_PACKET *) &(Que).First;}    \
	
//Test for empty queue macro.
#define IsPacketQueEmpty(Que)  (((Que).First) == (MINIPORT_PACKET *) 0)

//Add a packet to queue macro.
#define QuePacket(Que, _Packet)  {MINIPORT_PACKET *__Last = (Que).Last;   \
	_Packet->Next = (MINIPORT_PACKET *) 0;   \
__Last->Next = (Que).Last = _Packet;}

//Remove a packet from queue macro.
#define DequePacket(Que, Packet) {Packet = (Que).First;                                \
	if(((Que).First = Packet->Next) == (MINIPORT_PACKET *) 0) \
(Que).Last = (MINIPORT_PACKET *) &(Que).First;}        

//Sneak a look at the packet at the head of the queue macro.
#define PeekQue(Que, _Packet) {_Packet = (Que).First;}

//----------------------------------------------------------------

//Multicast Table Entry Structure
#define MAX_MULTICAST_ADDRESS	128

typedef struct _MULTICAST_TABLE
{
	UINT	MulticastTableEntryCount;
	UCHAR	MulticastTableEntry[MAX_MULTICAST_ADDRESS * ETH_LENGTH_OF_ADDRESS];
} MULTICAST_TABLE;


#define TOTAL_BUFFER_SIZE		0x2000
#define MAX_LOOKAHEAD_SIZE      1514
#define LOOK_AHEAD_BUFFER_SIZE  2048
#define MAX_FRAME_DATA_SIZE     1500
#define MAX_FRAME_SIZE          ((USHORT)1514)
#define MIN_FRAME_SIZE          14
#define MIN_LEGAL_FRAME_SIZE    64
#define ETHERNET_HEADER_SIZE    14
#define FRAME_OVERHEAD          6       //  Overhead bytes for adapter control
#define PTR_WAIT                5       //  Loop count waiting after pointer load
#define MAX_PACKETS				4
#define	PROT_RESERVED			0

#define AUTO_NEGOTIATION         0xFF
#define DEFAULT_VALUE            0xFE
#define FULL_DUPLEX              0x01
#define HALF_DUPLEX              0x00
#define SPEED10                  100000
#define SPEED100                 1000000

#define DEFAULT_IO_BASE         0x300   //  Platform Specific
#define DEFAULT_IRQ             10      //  Platform Specific
#define DEFAULT_MEDIA           0       //  Default media type


#define SANITY_CHECK 1
//--------------------- DRIVER STRUCTURE --------------------------------
#pragma pack(16)
typedef  struct _MINIPORT_ADAPTER
{
	NDIS_HANDLE				AdapterHandle;
	ULONG					IOBase;				//Platform Specific - type might have to be changed to accomodate platform specific values
	BOOLEAN					IsPortRegistered;	//I/O Port registere with NdisMRegisterIORage (...)
	NDIS_MINIPORT_INTERRUPT	InterruptInfo;		//From NdisMRegisterInterrupt(..)
	USHORT					InterruptLevel;		//IRQ in use
	BOOLEAN					IsInterruptSet;		//Attached to interrupt using NdisMRegisterInterrupt(...)
	USHORT					InterruptVector;
	BOOLEAN					Auto_Negotiation;
	USHORT					BusType;
	USHORT					BusNumber;
	USHORT					ConfigReg;			//Config register to be output
	USHORT					ChipID;				//Chip ID 
	USHORT					ChipRev;			//Chip Revision

	NDIS_HANDLE				PacketPool;				//Packet Pool
	NDIS_HANDLE				BufferPool;				//Buffer Pool
	PNDIS_PACKET			Packet[MAX_PACKETS];	//Array of packet descriptor pointers
	PNDIS_BUFFER			Buffer[MAX_PACKETS];	//Array of buffer descriptor pointers
	PUSHORT					LookAheadBuffer[MAX_PACKETS];	//Array of Pointers to lookahead buffer
	USHORT					State;				//Current state of the Adapter..
	NDIS_OID				LookAhead;			//Max lookahead size
	UINT					Speed;				//Speed ?? 10/100 
	UCHAR					Duplex;				//Duplex ?? FDX/HDX
	UCHAR					MACAddress[6];		//Current Station address
	USHORT					RCR;				//Updated Receive Control Register.
	USHORT					TCR;				//Updated Transmit Control Register.
	USHORT					CtrlRegister;

	USHORT					LinkStatus;			//Link Status
	BOOLEAN					NeedIndComplete;	//Recieve Complete indication
	BOOLEAN					RCVBroadcast;		//If set recvs broadcasts.
	BOOLEAN					RCVAllMulticast;	//Rcv All multicasts.
	BOOLEAN					PromiscuousMode;
	MULTICAST_TABLE			MulticastTable;		//Multicast Table
	UCHAR					HashTable[8];		//Multicast hash bits

	BOOLEAN					TxResPending;		//When set, NDISMResourceAvailable should be called
	MINIPORT_PACKET_QUE		AckPending;			//Waiting completion intr
	PUCHAR					TxBuffer;			//Pointer to the TX Copy buffer
		
	MINIPORT_PACKET_QUE		AllocPending;
	BOOLEAN					AllocIntPending;

	//Required Statistics.
	UINT					Stat_TxOK;
	UINT					Stat_RxOK;
	UINT					Stat_TxError;
	UINT					Stat_RxError;
	UINT					Stat_RxOvrn;
	UINT					Stat_AlignError;
	UINT					Stat_SingleColl;
	UINT					Stat_MultiColl;

#ifdef SANITY_CHECK
	UINT	AddQ, DelQ;
#endif

}MINIPORT_ADAPTER, *PMINIPORT_ADAPTER, *PSMSC_ADAPTER;
#define MINIPORT_ADAPTER_SIZE sizeof(MINIPORT_ADAPTER)


//-----------------  LAN91C111 Chip Specific Registry Declarations ---------

#define BANK_SELECT             14      //  Offset in IO space to Bank select
#define BANK_ID_MASK            0xff00  //  Mask constant part of bank register
#define BANK_UPPER              0x3300  //  Constant value for upper byte of bank register
#define BANK_MASK               (BANK_UPPER | 3)

//Bank 0 Registers
#define BANK0_TCR               0       //  Transmit control register
#define BANK0_STS               2       //  EPH status register 
#define BANK0_RCR               4       //  Receive control register
#define BANK0_CTR               6       //  Statistics counter register
#define BANK0_MIR               8       //  Memory information register
#define BANK0_RPCR              10      //  Memory configuration register
#define BANK0_RES               12      //  Reserved

//Bank 1 Registers
#define BANK1_CONFIG            0       //  Adapter configuration register
#define BANK1_BASE              2       //  IO Base address
#define BANK1_IA0               4       //  Current address bytes 0-1
#define BANK1_IA2               6       //  Current address bytes 2-3
#define BANK1_IA4               8       //  Current address bytes 4-5