mcf5275_fec.h

COLDFIRE 5275板极初始化程序

#define MCF_FEC_MSCR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x001044+((x)*0x800)]))
#define MCF_FEC_MIBC(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x001064+((x)*0x800)]))
#define MCF_FEC_RCR(x)                   (*(vuint32*)(void*)(&__IPSBAR[0x001084+((x)*0x800)]))
#define MCF_FEC_TCR(x)                   (*(vuint32*)(void*)(&__IPSBAR[0x0010C4+((x)*0x800)]))
#define MCF_FEC_PALR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x0010E4+((x)*0x800)]))
#define MCF_FEC_PAUR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x0010E8+((x)*0x800)]))
#define MCF_FEC_OPD(x)                   (*(vuint32*)(void*)(&__IPSBAR[0x0010EC+((x)*0x800)]))
#define MCF_FEC_IAUR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x001118+((x)*0x800)]))
#define MCF_FEC_IALR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x00111C+((x)*0x800)]))
#define MCF_FEC_GAUR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x001120+((x)*0x800)]))
#define MCF_FEC_GALR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x001124+((x)*0x800)]))
#define MCF_FEC_TFWR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x001144+((x)*0x800)]))
#define MCF_FEC_FRBR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x00114C+((x)*0x800)]))
#define MCF_FEC_FRSR(x)                  (*(vuint32*)(void*)(&__IPSBAR[0x001150+((x)*0x800)]))
#define MCF_FEC_ERDSR(x)                 (*(vuint32*)(void*)(&__IPSBAR[0x001180+((x)*0x800)]))
#define MCF_FEC_ETDSR(x)                 (*(vuint32*)(void*)(&__IPSBAR[0x001184+((x)*0x800)]))
#define MCF_FEC_EMRBR(x)                 (*(vuint32*)(void*)(&__IPSBAR[0x0011B8+((x)*0x800)]))
#define MCF_FEC_RMON_T_DROP(x)           (*(vuint32*)(void*)(&__IPSBAR[0x001200+((x)*0x800)]))
#define MCF_FEC_RMON_T_PACKETS(x)        (*(vuint32*)(void*)(&__IPSBAR[0x001204+((x)*0x800)]))
#define MCF_FEC_RMON_T_BC_PKT(x)         (*(vuint32*)(void*)(&__IPSBAR[0x001208+((x)*0x800)]))
#define MCF_FEC_RMON_T_MC_PKT(x)         (*(vuint32*)(void*)(&__IPSBAR[0x00120C+((x)*0x800)]))
#define MCF_FEC_RMON_T_CRC_ALIGN(x)      (*(vuint32*)(void*)(&__IPSBAR[0x001210+((x)*0x800)]))
#define MCF_FEC_RMON_T_UNDERSIZE(x)      (*(vuint32*)(void*)(&__IPSBAR[0x001214+((x)*0x800)]))
#define MCF_FEC_RMON_T_OVERSIZE(x)       (*(vuint32*)(void*)(&__IPSBAR[0x001218+((x)*0x800)]))
#define MCF_FEC_RMON_T_FRAG(x)           (*(vuint32*)(void*)(&__IPSBAR[0x00121C+((x)*0x800)]))
#define MCF_FEC_RMON_T_JAB(x)            (*(vuint32*)(void*)(&__IPSBAR[0x001220+((x)*0x800)]))
#define MCF_FEC_RMON_T_COL(x)            (*(vuint32*)(void*)(&__IPSBAR[0x001224+((x)*0x800)]))
#define MCF_FEC_RMON_T_P64(x)            (*(vuint32*)(void*)(&__IPSBAR[0x001228+((x)*0x800)]))
#define MCF_FEC_RMON_T_P65TO127(x)       (*(vuint32*)(void*)(&__IPSBAR[0x00122C+((x)*0x800)]))
#define MCF_FEC_RMON_T_P128TO255(x)      (*(vuint32*)(void*)(&__IPSBAR[0x001230+((x)*0x800)]))
#define MCF_FEC_RMON_T_P256TO511(x)      (*(vuint32*)(void*)(&__IPSBAR[0x001234+((x)*0x800)]))
#define MCF_FEC_RMON_T_P512TO1023(x)     (*(vuint32*)(void*)(&__IPSBAR[0x001238+((x)*0x800)]))
#define MCF_FEC_RMON_T_P1024TO2047(x)    (*(vuint32*)(void*)(&__IPSBAR[0x00123C+((x)*0x800)]))
#define MCF_FEC_RMON_T_P_GTE2048(x)      (*(vuint32*)(void*)(&__IPSBAR[0x001240+((x)*0x800)]))
#define MCF_FEC_RMON_T_OCTETS(x)         (*(vuint32*)(void*)(&__IPSBAR[0x001244+((x)*0x800)]))
#define MCF_FEC_IEEE_T_DROP(x)           (*(vuint32*)(void*)(&__IPSBAR[0x001248+((x)*0x800)]))
#define MCF_FEC_IEEE_T_FRAME_OK(x)       (*(vuint32*)(void*)(&__IPSBAR[0x00124C+((x)*0x800)]))
#define MCF_FEC_IEEE_T_1COL(x)           (*(vuint32*)(void*)(&__IPSBAR[0x001250+((x)*0x800)]))
#define MCF_FEC_IEEE_T_MCOL(x)           (*(vuint32*)(void*)(&__IPSBAR[0x001254+((x)*0x800)]))
#define MCF_FEC_IEEE_T_DEF(x)            (*(vuint32*)(void*)(&__IPSBAR[0x001258+((x)*0x800)]))
#define MCF_FEC_IEEE_T_LCOL(x)           (*(vuint32*)(void*)(&__IPSBAR[0x00125C+((x)*0x800)]))
#define MCF_FEC_IEEE_T_EXCOL(x)          (*(vuint32*)(void*)(&__IPSBAR[0x001260+((x)*0x800)]))
#define MCF_FEC_IEEE_T_MACERR(x)         (*(vuint32*)(void*)(&__IPSBAR[0x001264+((x)*0x800)]))
#define MCF_FEC_IEEE_T_CSERR(x)          (*(vuint32*)(void*)(&__IPSBAR[0x001268+((x)*0x800)]))
#define MCF_FEC_IEEE_T_SQE(x)            (*(vuint32*)(void*)(&__IPSBAR[0x00126C+((x)*0x800)]))
#define MCF_FEC_IEEE_T_FDXFC(x)          (*(vuint32*)(void*)(&__IPSBAR[0x001270+((x)*0x800)]))
#define MCF_FEC_IEEE_T_OCTETS_OK(x)      (*(vuint32*)(void*)(&__IPSBAR[0x001274+((x)*0x800)]))
#define MCF_FEC_RMON_R_PACKETS(x)        (*(vuint32*)(void*)(&__IPSBAR[0x001284+((x)*0x800)]))
#define MCF_FEC_RMON_R_BC_PKT(x)         (*(vuint32*)(void*)(&__IPSBAR[0x001288+((x)*0x800)]))
#define MCF_FEC_RMON_R_MC_PKT(x)         (*(vuint32*)(void*)(&__IPSBAR[0x00128C+((x)*0x800)]))
#define MCF_FEC_RMON_R_CRC_ALIGN(x)      (*(vuint32*)(void*)(&__IPSBAR[0x001290+((x)*0x800)]))
#define MCF_FEC_RMON_R_UNDERSIZE(x)      (*(vuint32*)(void*)(&__IPSBAR[0x001294+((x)*0x800)]))
#define MCF_FEC_RMON_R_OVERSIZE(x)       (*(vuint32*)(void*)(&__IPSBAR[0x001298+((x)*0x800)]))
#define MCF_FEC_RMON_R_FRAG(x)           (*(vuint32*)(void*)(&__IPSBAR[0x00129C+((x)*0x800)]))
#define MCF_FEC_RMON_R_JAB(x)            (*(vuint32*)(void*)(&__IPSBAR[0x0012A0+((x)*0x800)]))
#define MCF_FEC_RMON_R_RESVD_0(x)        (*(vuint32*)(void*)(&__IPSBAR[0x0012A4+((x)*0x800)]))
#define MCF_FEC_RMON_R_P64(x)            (*(vuint32*)(void*)(&__IPSBAR[0x0012A8+((x)*0x800)]))
#define MCF_FEC_RMON_R_P65TO127(x)       (*(vuint32*)(void*)(&__IPSBAR[0x0012AC+((x)*0x800)]))
#define MCF_FEC_RMON_R_P128TO255(x)      (*(vuint32*)(void*)(&__IPSBAR[0x0012B0+((x)*0x800)]))
#define MCF_FEC_RMON_R_P256TO511(x)      (*(vuint32*)(void*)(&__IPSBAR[0x0012B4+((x)*0x800)]))
#define MCF_FEC_RMON_R_512TO1023(x)      (*(vuint32*)(void*)(&__IPSBAR[0x0012B8+((x)*0x800)]))
#define MCF_FEC_RMON_R_P_GTE2048(x)      (*(vuint32*)(void*)(&__IPSBAR[0x0012C0+((x)*0x800)]))
#define MCF_FEC_RMON_R_1024TO2047(x)     (*(vuint32*)(void*)(&__IPSBAR[0x0012BC+((x)*0x800)]))
#define MCF_FEC_RMON_R_OCTETS(x)         (*(vuint32*)(void*)(&__IPSBAR[0x0012C4+((x)*0x800)]))
#define MCF_FEC_IEEE_R_DROP(x)           (*(vuint32*)(void*)(&__IPSBAR[0x0012C8+((x)*0x800)]))
#define MCF_FEC_IEEE_R_FRAME_OK(x)       (*(vuint32*)(void*)(&__IPSBAR[0x0012CC+((x)*0x800)]))
#define MCF_FEC_IEEE_R_CRC(x)            (*(vuint32*)(void*)(&__IPSBAR[0x0012D0+((x)*0x800)]))
#define MCF_FEC_IEEE_R_ALIGN(x)          (*(vuint32*)(void*)(&__IPSBAR[0x0012D4+((x)*0x800)]))
#define MCF_FEC_IEEE_R_MACERR(x)         (*(vuint32*)(void*)(&__IPSBAR[0x0012D8+((x)*0x800)]))
#define MCF_FEC_IEEE_R_FDXFC(x)          (*(vuint32*)(void*)(&__IPSBAR[0x0012DC+((x)*0x800)]))
#define MCF_FEC_IEEE_R_OCTETS_OK(x)      (*(vuint32*)(void*)(&__IPSBAR[0x0012E0+((x)*0x800)]))

/* Bit definitions and macros for MCF_FEC_EIR */
#define MCF_FEC_EIR_UN                  (0x00080000)
#define MCF_FEC_EIR_RL                  (0x00100000)
#define MCF_FEC_EIR_LC                  (0x00200000)
#define MCF_FEC_EIR_EBERR               (0x00400000)
#define MCF_FEC_EIR_MII                 (0x00800000)
#define MCF_FEC_EIR_RXB                 (0x01000000)
#define MCF_FEC_EIR_RXF                 (0x02000000)
#define MCF_FEC_EIR_TXB                 (0x04000000)
#define MCF_FEC_EIR_TXF                 (0x08000000)
#define MCF_FEC_EIR_GRA                 (0x10000000)
#define MCF_FEC_EIR_BABT                (0x20000000)
#define MCF_FEC_EIR_BABR                (0x40000000)
#define MCF_FEC_EIR_HBERR               (0x80000000)

/* Bit definitions and macros for MCF_FEC_EIMR */
#define MCF_FEC_EIMR_UN                 (0x00080000)
#define MCF_FEC_EIMR_RL                 (0x00100000)
#define MCF_FEC_EIMR_LC                 (0x00200000)
#define MCF_FEC_EIMR_EBERR              (0x00400000)
#define MCF_FEC_EIMR_MII                (0x00800000)
#define MCF_FEC_EIMR_RXB                (0x01000000)
#define MCF_FEC_EIMR_RXF                (0x02000000)
#define MCF_FEC_EIMR_TXB                (0x04000000)
#define MCF_FEC_EIMR_TXF                (0x08000000)
#define MCF_FEC_EIMR_GRA                (0x10000000)
#define MCF_FEC_EIMR_BABT               (0x20000000)
#define MCF_FEC_EIMR_BABR               (0x40000000)
#define MCF_FEC_EIMR_HBERR              (0x80000000)

/* Bit definitions and macros for MCF_FEC_RDAR */
#define MCF_FEC_RDAR_R_DES_ACTIVE       (0x01000000)

/* Bit definitions and macros for MCF_FEC_TDAR */
#define MCF_FEC_TDAR_X_DES_ACTIVE       (0x01000000)

/* Bit definitions and macros for MCF_FEC_ECR */
#define MCF_FEC_ECR_RESET               (0x00000001)
#define MCF_FEC_ECR_ETHER_EN            (0x00000002)

/* Bit definitions and macros for MCF_FEC_MMFR */
#define MCF_FEC_MMFR_DATA(x)            (((x)&0x0000FFFF)<<0)
#define MCF_FEC_MMFR_TA(x)              (((x)&0x00000003)<<16)
#define MCF_FEC_MMFR_RA(x)              (((x)&0x0000001F)<<18)
#define MCF_FEC_MMFR_PA(x)              (((x)&0x0000001F)<<23)
#define MCF_FEC_MMFR_OP(x)              (((x)&0x00000003)<<28)
#define MCF_FEC_MMFR_ST(x)              (((x)&0x00000003)<<30)
#define MCF_FEC_MMFR_ST_01              (0x40000000)
#define MCF_FEC_MMFR_OP_READ            (0x20000000)
#define MCF_FEC_MMFR_OP_WRITE           (0x10000000)
#define MCF_FEC_MMFR_TA_10              (0x00020000)

/* Bit definitions and macros for MCF_FEC_MSCR */
#define MCF_FEC_MSCR_MII_SPEED(x)       (((x)&0x0000003F)<<1)
#define MCF_FEC_MSCR_DIS_PREAMBLE       (0x00000080)

/* Bit definitions and macros for MCF_FEC_MIBC */
#define MCF_FEC_MIBC_MIB_IDLE           (0x40000000)
#define MCF_FEC_MIBC_MIB_DISABLE        (0x80000000)

/* Bit definitions and macros for MCF_FEC_RCR */
#define MCF_FEC_RCR_LOOP                (0x00000001)
#define MCF_FEC_RCR_DRT                 (0x00000002)
#define MCF_FEC_RCR_MII_MODE            (0x00000004)
#define MCF_FEC_RCR_PROM                (0x00000008)
#define MCF_FEC_RCR_BC_REJ              (0x00000010)
#define MCF_FEC_RCR_FCE                 (0x00000020)
#define MCF_FEC_RCR_MAX_FL(x)           (((x)&0x000007FF)<<16)

/* Bit definitions and macros for MCF_FEC_TCR */
#define MCF_FEC_TCR_GTS                 (0x00000001)
#define MCF_FEC_TCR_HBC                 (0x00000002)
#define MCF_FEC_TCR_FDEN                (0x00000004)
#define MCF_FEC_TCR_TFC_PAUSE           (0x00000008)
#define MCF_FEC_TCR_RFC_PAUSE           (0x00000010)

/* Bit definitions and macros for MCF_FEC_PAUR */
#define MCF_FEC_PAUR_TYPE(x)            (((x)&0x0000FFFF)<<0)
#define MCF_FEC_PAUR_PADDR2(x)          (((x)&0x0000FFFF)<<16)

/* Bit definitions and macros for MCF_FEC_OPD */
#define MCF_FEC_OPD_PAUSE_DUR(x)        (((x)&0x0000FFFF)<<0)
#define MCF_FEC_OPD_OPCODE(x)           (((x)&0x0000FFFF)<<16)

/* Bit definitions and macros for MCF_FEC_TFWR */
#define MCF_FEC_TFWR_X_WMRK(x)          (((x)&0x00000003)<<0)

/* Bit definitions and macros for MCF_FEC_FRBR */
#define MCF_FEC_FRBR_R_BOUND(x)         (((x)&0x000000FF)<<2)

/* Bit definitions and macros for MCF_FEC_FRSR */
#define MCF_FEC_FRSR_R_FSTART(x)        (((x)&0x000000FF)<<2)

/* Bit definitions and macros for MCF_FEC_ERDSR */
#define MCF_FEC_ERDSR_R_DES_START(x)    (((x)&0x3FFFFFFF)<<2)

/* Bit definitions and macros for MCF_FEC_ETDSR */
#define MCF_FEC_ETDSR_X_DES_START(x)    (((x)&0x3FFFFFFF)<<2)

/* Bit definitions and macros for MCF_FEC_EMRBR */
#define MCF_FEC_EMRBR_R_BUF_SIZE(x)     (((x)&0x0000007F)<<4)

/********************************************************************/

#endif /* __MCF5275_FEC_H__ */