mcf5275_sdramc.h

COLDFIRE 5275板极初始化程序

/*
 * File:	mcf5275_sdramc.h
 * Purpose:	Register and bit definitions for the MCF5275
 *
 * Notes:	
 *	
 */

#ifndef __MCF5275_SDRAMC_H__
#define __MCF5275_SDRAMC_H__

/*********************************************************************
*
* SDRAM Controller (SDRAMC)
*
*********************************************************************/

/* Register read/write macros */
#define MCF_SDRAMC_SDMR      (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
#define MCF_SDRAMC_SDCR      (*(vuint32*)(void*)(&__IPSBAR[0x000044]))
#define MCF_SDRAMC_SDCFG1    (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
#define MCF_SDRAMC_SDCFG2    (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
#define MCF_SDRAMC_SDBAR0    (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
#define MCF_SDRAMC_SDBAR1    (*(vuint32*)(void*)(&__IPSBAR[0x000058]))
#define MCF_SDRAMC_SDMR0     (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
#define MCF_SDRAMC_SDMR1     (*(vuint32*)(void*)(&__IPSBAR[0x00005C]))

/* Bit definitions and macros for MCF_SDRAMC_SDMR */
#define MCF_SDRAMC_SDMR_CMD             (0x00010000)
#define MCF_SDRAMC_SDMR_AD(x)           (((x)&0x00000FFF)<<18)
#define MCF_SDRAMC_SDMR_BNKAD(x)        (((x)&0x00000003)<<30)
#define MCF_SDRAMC_SDMR_BNKAD_LMR       (0x00000000)
#define MCF_SDRAMC_SDMR_BNKAD_LEMR      (0x40000000)

/* Bit definitions and macros for MCF_SDRAMC_SDCR */
#define MCF_SDRAMC_SDCR_IPALL           (0x00000002)
#define MCF_SDRAMC_SDCR_IREF            (0x00000004)
#define MCF_SDRAMC_SDCR_DQS_OE(x)       (((x)&0x00000003)<<10)
#define MCF_SDRAMC_SDCR_DQP_BP          (0x00008000)
#define MCF_SDRAMC_SDCR_RCNT(x)         (((x)&0x0000003F)<<16)
#define MCF_SDRAMC_SDCR_MUX(x)          (((x)&0x00000003)<<24)
#define MCF_SDRAMC_SDCR_REF             (0x10000000)
#define MCF_SDRAMC_SDCR_CKE             (0x40000000)
#define MCF_SDRAMC_SDCR_MODE_EN         (0x80000000)

/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
#define MCF_SDRAMC_SDCFG1_WTLAT(x)      (((x)&0x00000007)<<4)
#define MCF_SDRAMC_SDCFG1_REF2ACT(x)    (((x)&0x0000000F)<<8)
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)    (((x)&0x00000007)<<12)
#define MCF_SDRAMC_SDCFG1_ACT2RW(x)     (((x)&0x00000007)<<16)
#define MCF_SDRAMC_SDCFG1_RDLAT(x)      (((x)&0x0000000F)<<20)
#define MCF_SDRAMC_SDCFG1_SWT2RD(x)     (((x)&0x00000007)<<24)
#define MCF_SDRAMC_SDCFG1_SRD2RW(x)     (((x)&0x0000000F)<<28)

/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
#define MCF_SDRAMC_SDCFG2_BL(x)         (((x)&0x0000000F)<<16)
#define MCF_SDRAMC_SDCFG2_BRD2WT(x)     (((x)&0x0000000F)<<20)
#define MCF_SDRAMC_SDCFG2_BWT2RW(x)     (((x)&0x0000000F)<<24)
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)    (((x)&0x0000000F)<<28)

/* Bit definitions and macros for MCF_SDRAMC_SDBARn */
#define MCF_SDRAMC_SDBARn_BASE(x)       (((x)&0x00003FFF)<<18)
#define MCF_SDRAMC_SDBARn_BA(x)         ((x)&0xFFFF0000)

/* Bit definitions and macros for MCF_SDRAMC_SDMRn */
#define MCF_SDRAMC_SDMRn_V              (0x00000001)
#define MCF_SDRAMC_SDMRn_WP             (0x00000080)
#define MCF_SDRAMC_SDMRn_MASK(x)        (((x)&0x00003FFF)<<18)
#define MCF_SDRAMC_SDMRn_BAM_4G         (0xFFFF0000)
#define MCF_SDRAMC_SDMRn_BAM_2G         (0x7FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_1G         (0x3FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_1024M      (0x3FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_512M       (0x1FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_256M       (0x0FFF0000)
#define MCF_SDRAMC_SDMRn_BAM_128M       (0x07FF0000)
#define MCF_SDRAMC_SDMRn_BAM_64M        (0x03FF0000)
#define MCF_SDRAMC_SDMRn_BAM_32M        (0x01FF0000)
#define MCF_SDRAMC_SDMRn_BAM_16M        (0x00FF0000)
#define MCF_SDRAMC_SDMRn_BAM_8M         (0x007F0000)
#define MCF_SDRAMC_SDMRn_BAM_4M         (0x003F0000)
#define MCF_SDRAMC_SDMRn_BAM_2M         (0x001F0000)
#define MCF_SDRAMC_SDMRn_BAM_1M         (0x000F0000)
#define MCF_SDRAMC_SDMRn_BAM_1024K      (0x000F0000)
#define MCF_SDRAMC_SDMRn_BAM_512K       (0x00070000)
#define MCF_SDRAMC_SDMRn_BAM_256K       (0x00030000)
#define MCF_SDRAMC_SDMRn_BAM_128K       (0x00010000)
#define MCF_SDRAMC_SDMRn_BAM_64K        (0x00000000)

/********************************************************************/

#endif /* __MCF5275_SDRAMC_H__ */