📄 mpc5xx.h
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/*
* File: dbug/src/cpu/ppc/mpc5xx/mpc5xx.h
* Purpose: Definitions for MPC5XX dBUG
*
* Notes:
*
* Modifications:
*
*/
#ifndef _DBUG_CPU_MPC5XX_H
#define _DBUG_CPU_MPC5XX_H
/***********************************************************************/
/*
* Common MPC5XX definitions for dBUG
*/
#define ADDRESS uint32
#define INSTRUCTION uint32
#define ILLEGAL 0x00000000
#define CPU_WORD_SIZE 32
/* Maximum number of software breakpoints */
#define UIF_MAX_HBRKPTS (4)
/*
* Registers data structure used for context saving and restoring.
*/
typedef struct
{
uint32 r0, r1, r2, r3, r4, r5, r6, r7; //these are all place holders
uint32 r8, r9, r10, r11, r12, r13, r14, r15; //names are never used anywhere
uint32 r16, r17, r18, r19, r20, r21, r22, r23;
uint32 r24, r25, r26, r27, r28, r29, r30, r31;
uint32 cr;
uint32 msr;
uint32 xer, lr, ctr, dsisr, dar, dec;
uint32 srr0, srr1, pvr, tbl, tbu;
uint32 sprg0, sprg1, sprg2, sprg3;
uint32 eie, eid, nri, cmpa, cmpb, cmpc;
uint32 cmpd, ecr, der, counta, countb, cmpe;
uint32 cmpf, cmpg, cmph, lctrl1, lctrl2, ictrl;
uint32 bar, mi_gra, l2u_gra, dpdr, immr;
uint32 bbcmcr, l2u_mcr;
uint32 mi_rba0, mi_rba1, mi_rba2, mi_rba3, mi_ra0;
uint32 mi_ra1, mi_ra2, mi_ra3, l2u_rba0, l2u_rba1, l2u_rba2, l2u_rba3;
uint32 l2u_ra0, l2u_ra1, l2u_ra2, l2u_ra3, fpecr, fpscr;
uint32 fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7;
uint32 fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15;
uint32 fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23;
uint32 fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31;
} REGISTERS;
/*
* Because ANSI C doesn't specify how members of a structure/array are
* stored, use a compiler independent method for accessing the registers.
* The 'registers' data structure is filled in by mpc8xx_lo.s
*/
#define Mpc5xx_reg(OFFSET) \
*(uint32 *)(&((uint8 *)&context)[OFFSET])
#define MPC5XX_R0 0 //now assigning names to the spaces we just set aside
#define MPC5XX_R1 4
#define MPC5XX_R2 8
#define MPC5XX_R3 12
#define MPC5XX_R4 16
#define MPC5XX_R5 20
#define MPC5XX_R6 24
#define MPC5XX_R7 28
#define MPC5XX_R8 32
#define MPC5XX_R9 36
#define MPC5XX_R10 40
#define MPC5XX_R11 44
#define MPC5XX_R12 48
#define MPC5XX_R13 52
#define MPC5XX_R14 56
#define MPC5XX_R15 60
#define MPC5XX_R16 64
#define MPC5XX_R17 68
#define MPC5XX_R18 72
#define MPC5XX_R19 76
#define MPC5XX_R20 80
#define MPC5XX_R21 84
#define MPC5XX_R22 88
#define MPC5XX_R23 92
#define MPC5XX_R24 96
#define MPC5XX_R25 100
#define MPC5XX_R26 104
#define MPC5XX_R27 108
#define MPC5XX_R28 112
#define MPC5XX_R29 116
#define MPC5XX_R30 120
#define MPC5XX_R31 124
#define MPC5XX_MSR 128
#define MPC5XX_CR 132
#define MPC5XX_XER 136
#define MPC5XX_LR 140
#define MPC5XX_CTR 144
#define MPC5XX_DSISR 148
#define MPC5XX_DAR 152
#define MPC5XX_DEC 156
#define MPC5XX_SRR0 160
#define MPC5XX_SRR1 164
#define MPC5XX_PVR 168
#define MPC5XX_TBL 172
#define MPC5XX_TBU 176
#define MPC5XX_SPRG0 180
#define MPC5XX_SPRG1 184
#define MPC5XX_SPRG2 188
#define MPC5XX_SPRG3 192
#define MPC5XX_EIE 196
#define MPC5XX_EID 200
#define MPC5XX_NRI 204
#define MPC5XX_CMPA 208
#define MPC5XX_CMPB 212
#define MPC5XX_CMPC 216
#define MPC5XX_CMPD 220
#define MPC5XX_ECR 224
#define MPC5XX_DER 228
#define MPC5XX_COUNTA 232
#define MPC5XX_COUNTB 236
#define MPC5XX_CMPE 240
#define MPC5XX_CMPF 244
#define MPC5XX_CMPG 248
#define MPC5XX_CMPH 252
#define MPC5XX_LCTRL1 256
#define MPC5XX_LCTRL2 260
#define MPC5XX_ICTRL 264
#define MPC5XX_BAR 268
#define MPC5XX_MI_GRA 272
#define MPC5XX_L2U_GRA 276
#define MPC5XX_DPDR 280
#define MPC5XX_IMMR 284
#define MPC5XX_BBCMCR 288
#define MPC5XX_L2U_MCR 292
#define MPC5XX_MI_RBA0 296
#define MPC5XX_MI_RBA1 300
#define MPC5XX_MI_RBA2 304
#define MPC5XX_MI_RBA3 308
#define MPC5XX_MI_RA0 312
#define MPC5XX_MI_RA1 316
#define MPC5XX_MI_RA2 320
#define MPC5XX_MI_RA3 324
#define MPC5XX_L2U_RBA0 328
#define MPC5XX_L2U_RBA1 332
#define MPC5XX_L2U_RBA2 336
#define MPC5XX_L2U_RBA3 340
#define MPC5XX_L2U_RA0 344
#define MPC5XX_L2U_RA1 348
#define MPC5XX_L2U_RA2 352
#define MPC5XX_L2U_RA3 356
#define MPC5XX_FPECR 360
#define MPC5XX_FPSCR 492
#define MPC5XX_FPR0 364
#define MPC5XX_FPR1 368
#define MPC5XX_FPR2 372
#define MPC5XX_FPR3 376
#define MPC5XX_FPR4 380
#define MPC5XX_FPR5 384
#define MPC5XX_FPR6 388
#define MPC5XX_FPR7 392
#define MPC5XX_FPR8 396
#define MPC5XX_FPR9 400
#define MPC5XX_FPR10 404
#define MPC5XX_FPR11 408
#define MPC5XX_FPR12 412
#define MPC5XX_FPR13 416
#define MPC5XX_FPR14 420
#define MPC5XX_FPR15 424
#define MPC5XX_FPR16 428
#define MPC5XX_FPR17 432
#define MPC5XX_FPR18 436
#define MPC5XX_FPR19 440
#define MPC5XX_FPR20 444
#define MPC5XX_FPR21 448
#define MPC5XX_FPR22 452
#define MPC5XX_FPR23 456
#define MPC5XX_FPR24 460
#define MPC5XX_FPR25 464
#define MPC5XX_FPR26 468
#define MPC5XX_FPR27 472
#define MPC5XX_FPR28 476
#define MPC5XX_FPR29 480
#define MPC5XX_FPR30 484
#define MPC5XX_FPR31 488
#define CPU_REG_R0 Mpc5xx_reg(MPC5XX_R0)
#define CPU_REG_R1 Mpc5xx_reg(MPC5XX_R1)
#define CPU_REG_R2 Mpc5xx_reg(MPC5XX_R2)
#define CPU_REG_R3 Mpc5xx_reg(MPC5XX_R3)
#define CPU_REG_R4 Mpc5xx_reg(MPC5XX_R4)
#define CPU_REG_R5 Mpc5xx_reg(MPC5XX_R5)
#define CPU_REG_R6 Mpc5xx_reg(MPC5XX_R6)
#define CPU_REG_R7 Mpc5xx_reg(MPC5XX_R7)
#define CPU_REG_R8 Mpc5xx_reg(MPC5XX_R8)
#define CPU_REG_R9 Mpc5xx_reg(MPC5XX_R9)
#define CPU_REG_R10 Mpc5xx_reg(MPC5XX_R10)
#define CPU_REG_R11 Mpc5xx_reg(MPC5XX_R11)
#define CPU_REG_R12 Mpc5xx_reg(MPC5XX_R12)
#define CPU_REG_R13 Mpc5xx_reg(MPC5XX_R13)
#define CPU_REG_R14 Mpc5xx_reg(MPC5XX_R14)
#define CPU_REG_R15 Mpc5xx_reg(MPC5XX_R15)
#define CPU_REG_R16 Mpc5xx_reg(MPC5XX_R16)
#define CPU_REG_R17 Mpc5xx_reg(MPC5XX_R17)
#define CPU_REG_R18 Mpc5xx_reg(MPC5XX_R18)
#define CPU_REG_R19 Mpc5xx_reg(MPC5XX_R19)
#define CPU_REG_R20 Mpc5xx_reg(MPC5XX_R20)
#define CPU_REG_R21 Mpc5xx_reg(MPC5XX_R21)
#define CPU_REG_R22 Mpc5xx_reg(MPC5XX_R22)
#define CPU_REG_R23 Mpc5xx_reg(MPC5XX_R23)
#define CPU_REG_R24 Mpc5xx_reg(MPC5XX_R24)
#define CPU_REG_R25 Mpc5xx_reg(MPC5XX_R25)
#define CPU_REG_R26 Mpc5xx_reg(MPC5XX_R26)
#define CPU_REG_R27 Mpc5xx_reg(MPC5XX_R27)
#define CPU_REG_R28 Mpc5xx_reg(MPC5XX_R28)
#define CPU_REG_R29 Mpc5xx_reg(MPC5XX_R29)
#define CPU_REG_R30 Mpc5xx_reg(MPC5XX_R30)
#define CPU_REG_R31 Mpc5xx_reg(MPC5XX_R31)
#define CPU_REG_MSR Mpc5xx_reg(MPC5XX_MSR)
#define CPU_REG_CR Mpc5xx_reg(MPC5XX_CR)
#define CPU_REG_XER Mpc5xx_reg(MPC5XX_XER)
#define CPU_REG_LR Mpc5xx_reg(MPC5XX_LR)
#define CPU_REG_CTR Mpc5xx_reg(MPC5XX_CTR)
#define CPU_REG_DSISR Mpc5xx_reg(MPC5XX_DSISR)
#define CPU_REG_DAR Mpc5xx_reg(MPC5XX_DAR)
#define CPU_REG_DEC Mpc5xx_reg(MPC5XX_DEC)
#define CPU_REG_SRR0 Mpc5xx_reg(MPC5XX_SRR0)
#define CPU_REG_SRR1 Mpc5xx_reg(MPC5XX_SRR1)
#define CPU_REG_PVR Mpc5xx_reg(MPC5XX_PVR)
#define CPU_REG_TBL Mpc5xx_reg(MPC5XX_TBL)
#define CPU_REG_TBU Mpc5xx_reg(MPC5XX_TBU)
#define CPU_REG_SPRG0 Mpc5xx_reg(MPC5XX_SPRG0)
#define CPU_REG_SPRG1 Mpc5xx_reg(MPC5XX_SPRG1)
#define CPU_REG_SPRG2 Mpc5xx_reg(MPC5XX_SPRG2)
#define CPU_REG_SPRG3 Mpc5xx_reg(MPC5XX_SPRG3)
#define CPU_REG_EIE Mpc5xx_reg(MPC5XX_EIE)
#define CPU_REG_EID Mpc5xx_reg(MPC5XX_EID)
#define CPU_REG_NRI Mpc5xx_reg(MPC5XX_NRI)
#define CPU_REG_CMPA Mpc5xx_reg(MPC5XX_CMPA)
#define CPU_REG_CMPB Mpc5xx_reg(MPC5XX_CMPB)
#define CPU_REG_CMPC Mpc5xx_reg(MPC5XX_CMPC)
#define CPU_REG_CMPD Mpc5xx_reg(MPC5XX_CMPD)
#define CPU_REG_ECR Mpc5xx_reg(MPC5XX_ECR)
#define CPU_REG_DER Mpc5xx_reg(MPC5XX_DER)
#define CPU_REG_COUNTA Mpc5xx_reg(MPC5XX_COUNTA)
#define CPU_REG_COUNTB Mpc5xx_reg(MPC5XX_COUNTB)
#define CPU_REG_CMPE Mpc5xx_reg(MPC5XX_CMPE)
#define CPU_REG_CMPF Mpc5xx_reg(MPC5XX_CMPF)
#define CPU_REG_CMPG Mpc5xx_reg(MPC5XX_CMPG)
#define CPU_REG_CMPH Mpc5xx_reg(MPC5XX_CMPH)
#define CPU_REG_LCTRL1 Mpc5xx_reg(MPC5XX_LCTRL1)
#define CPU_REG_LCTRL2 Mpc5xx_reg(MPC5XX_LCTRL2)
#define CPU_REG_ICTRL Mpc5xx_reg(MPC5XX_ICTRL)
#define CPU_REG_BAR Mpc5xx_reg(MPC5XX_BAR)
#define CPU_REG_MI_GRA Mpc5xx_reg(MPC5XX_MI_GRA)
#define CPU_REG_L2U_GRA Mpc5xx_reg(MPC5XX_L2U_GRA)
#define CPU_REG_DPDR Mpc5xx_reg(MPC5XX_DPDR)
#define CPU_REG_IMMR Mpc5xx_reg(MPC5XX_IMMR)
#define CPU_REG_BBCMCR Mpc5xx_reg(MPC5XX_BBCMCR)
#define CPU_REG_L2U_MCR Mpc5xx_reg(MPC5XX_L2U_MCR)
#define CPU_REG_MI_RBA0 Mpc5xx_reg(MPC5XX_MI_RBA0)
#define CPU_REG_MI_RBA1 Mpc5xx_reg(MPC5XX_MI_RBA1)
#define CPU_REG_MI_RBA2 Mpc5xx_reg(MPC5XX_MI_RBA2)
#define CPU_REG_MI_RBA3 Mpc5xx_reg(MPC5XX_MI_RBA3)
#define CPU_REG_RA0 Mpc5xx_reg(MPC5XX_RA0)
#define CPU_REG_RA1 Mpc5xx_reg(MPC5XX_RA1)
#define CPU_REG_RA2 Mpc5xx_reg(MPC5XX_RA2)
#define CPU_REG_RA3 Mpc5xx_reg(MPC5XX_RA3)
#define CPU_REG_L2U_RBA0 Mpc5xx_reg(MPC5XX_L2U_RBA0)
#define CPU_REG_L2U_RBA1 Mpc5xx_reg(MPC5XX_L2U_RBA1)
#define CPU_REG_L2U_RBA2 Mpc5xx_reg(MPC5XX_L2U_RBA2)
#define CPU_REG_L2U_RBA3 Mpc5xx_reg(MPC5XX_L2U_RBA3)
#define CPU_REG_L2U_RA0 Mpc5xx_reg(MPC5XX_L2U_RA0)
#define CPU_REG_L2U_RA1 Mpc5xx_reg(MPC5XX_L2U_RA1)
#define CPU_REG_L2U_RA2 Mpc5xx_reg(MPC5XX_L2U_RA2)
#define CPU_REG_L2U_RA3 Mpc5xx_reg(MPC5XX_L2U_RA3)
#define CPU_REG_FPECR Mpc5xx_reg(MPC5XX_FPECR)
#define CPU_REG_FPSCR Mpc5xx_reg(MPC5XX_FPSCR)
#define CPU_REG_FPR0 Mpc5xx_reg(MPC5XX_FPR0)
#define CPU_REG_FPR1 Mpc5xx_reg(MPC5XX_FPR1)
#define CPU_REG_FPR2 Mpc5xx_reg(MPC5XX_FPR2)
#define CPU_REG_FPR3 Mpc5xx_reg(MPC5XX_FPR3)
#define CPU_REG_FPR4 Mpc5xx_reg(MPC5XX_FPR4)
#define CPU_REG_FPR5 Mpc5xx_reg(MPC5XX_FPR5)
#define CPU_REG_FPR6 Mpc5xx_reg(MPC5XX_FPR6)
#define CPU_REG_FPR7 Mpc5xx_reg(MPC5XX_FPR7)
#define CPU_REG_FPR8 Mpc5xx_reg(MPC5XX_FPR8)
#define CPU_REG_FPR9 Mpc5xx_reg(MPC5XX_FPR9)
#define CPU_REG_FPR10 Mpc5xx_reg(MPC5XX_FPR10)
#define CPU_REG_FPR11 Mpc5xx_reg(MPC5XX_FPR11)
#define CPU_REG_FPR12 Mpc5xx_reg(MPC5XX_FPR12)
#define CPU_REG_FPR13 Mpc5xx_reg(MPC5XX_FPR13)
#define CPU_REG_FPR14 Mpc5xx_reg(MPC5XX_FPR14)
#define CPU_REG_FPR15 Mpc5xx_reg(MPC5XX_FPR15)
#define CPU_REG_FPR16 Mpc5xx_reg(MPC5XX_FPR16)
#define CPU_REG_FPR17 Mpc5xx_reg(MPC5XX_FPR17)
#define CPU_REG_FPR18 Mpc5xx_reg(MPC5XX_FPR18)
#define CPU_REG_FPR19 Mpc5xx_reg(MPC5XX_FPR19)
#define CPU_REG_FPR20 Mpc5xx_reg(MPC5XX_FPR20)
#define CPU_REG_FPR21 Mpc5xx_reg(MPC5XX_FPR21)
#define CPU_REG_FPR22 Mpc5xx_reg(MPC5XX_FPR22)
#define CPU_REG_FPR23 Mpc5xx_reg(MPC5XX_FPR23)
#define CPU_REG_FPR24 Mpc5xx_reg(MPC5XX_FPR24)
#define CPU_REG_FPR25 Mpc5xx_reg(MPC5XX_FPR25)
#define CPU_REG_FPR26 Mpc5xx_reg(MPC5XX_FPR26)
#define CPU_REG_FPR27 Mpc5xx_reg(MPC5XX_FPR27)
#define CPU_REG_FPR28 Mpc5xx_reg(MPC5XX_FPR28)
#define CPU_REG_FPR29 Mpc5xx_reg(MPC5XX_FPR29)
#define CPU_REG_FPR30 Mpc5xx_reg(MPC5XX_FPR30)
#define CPU_REG_FPR31 Mpc5xx_reg(MPC5XX_FPR31)
/***********************************************************************/
/*
* Prototypes for routines invoked by MPC5XX dBUG.
*/
void *
mpc5xx_isb (void);
void
asm_switch_context (void *);
void
asm_return_from_call (void);
void
mpc5xx_rsr_display (void);
char *
cpu_get_spr_name (int);
void
mpc5xx_call (int, char **);
void
mpc5xx_ird (int, char **);
void
mpc5xx_irm (int, char **);
void
mpc5xx_hbr (int, char **);
/***********************************************************************/
#define CPU_CMD_CALL \
{"call",4,1,UIF_MAX_ARGS,1,mpc5xx_call, "Call Subroutine", "addr <args>"},
#define CPU_CMD_IRD \
{"ird",3,0,1,0,mpc5xx_ird, "Internal Reg Display", "<module.register>"},
#define CPU_CMD_IRM \
{"irm",3,2,2,0,mpc5xx_irm, "Internal Reg Modify", "module.register data"},
#define CPU_CMD_HBR \
{"hbr",2,0,UIF_MAX_ARGS,0,mpc5xx_hbr, "Hardware Breakpoint", "module.register data"},
#define CPU_CMDS_ALL \
CPU_CMD_CALL \
CPU_CMD_IRD \
CPU_CMD_IRM \
CPU_CMD_HBR
#define CPU_SETCMDS_ALL
/***********************************************************************/
#endif /* _DBUG_CPU_MPC5XX_H */
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