mpc5xx_hi.c

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

    IRMD(MIOS14, MDASM29AR,     16)
    IRMD(MIOS14, MDASM29BR,     16)
    IRMD(MIOS14, MDASM29SCR,    16)
    IRMD(MIOS14, MDASM30AR,     16)
    IRMD(MIOS14, MDASM30BR,     16)
    IRMD(MIOS14, MDASM30SCR,    16)
    IRMD(MIOS14, MDASM31AR,     16)
    IRMD(MIOS14, MDASM31BR,     16)
    IRMD(MIOS14, MDASM31SCR,    16)
    IRMD(MIOS14, MPIOSM32DR,    16)
    IRMD(MIOS14, MPIOSM32DDR,   16)
    IRMD(MIOS14, MIOS14TPCR,    16)
    IRMD(MIOS14, MIOS14VECT,    16)
    IRMD(MIOS14, MIOS14VNR,     16)
    IRMD(MIOS14, MIOS14MCR,     16)
    IRMD(MIOS14, MCPSMSCR,      16)
    IRMD(MIOS14, MIOS14SR0,     16)
    IRMD(MIOS14, MIOS14ER0,     16)
    IRMD(MIOS14, MIOS14RPR0,    16)
    IRMD(MIOS14, MIOS14LVL0,    16)
    IRMD(MIOS14, MIOS14SR1,     16)
    IRMD(MIOS14, MIOS14ER1,     16)
    IRMD(MIOS14, MIOS14RPR1,    16)
    IRMD(MIOS14, MIOS14LVL1,    16)
}
#endif

/*********************************************************************/
#ifdef CPU_MPC555
/*
 * The MPC555 has one 6K DPTRAM
 */
static void
irmd_dptram (char *reg, int regread, uint32 value)
{
    IRMD(DPTRAM, DPTMCR,    16)
    IRMD(DPTRAM, RAMBAR,    16)
    IRMD(DPTRAM, MISRH,     16)
    IRMD(DPTRAM, MISRL,     16)
    IRMD(DPTRAM, MISCNT,    16)
}
#endif

/*********************************************************************/
#if (defined (CPU_MPC561) || defined (CPU_MPC562) || \
     defined (CPU_MPC563) || defined (CPU_MPC564))
/*
 * The MPC561/2/3/4 have one 8K DPTRAM
 */
static void
irmd_dptram8k (char *reg, int regread, uint32 value)
{
    IRMD(DPTRAM8K, DPTMCR,  16)
    IRMD(DPTRAM8K, RAMBAR,  16)
    IRMD(DPTRAM8K, MISRH,   16)
    IRMD(DPTRAM8K, MISRL,   16)
    IRMD(DPTRAM8K, MISCNT,  16)
}
#endif

/*********************************************************************/
#if (defined (CPU_MPC565) || defined (CPU_MPC566))
/*
 * The MPC565/6 have one 6K DPTRAM and one 4K DPTRAM
 */
static void
irmd_dptram6k (char *reg, int regread, uint32 value)
{
    IRMD(DPTRAM6K, DPTMCR,  16)
    IRMD(DPTRAM6K, RAMBAR,  16)
    IRMD(DPTRAM6K, MISRH,   16)
    IRMD(DPTRAM6K, MISRL,   16)
    IRMD(DPTRAM6K, MISCNT,  16)
}
static void
irmd_dptram4k (char *reg, int regread, uint32 value)
{
    IRMD(DPTRAM4K, DPTMCR,  16)
    IRMD(DPTRAM4K, RAMTST,  16)
    IRMD(DPTRAM4K, RAMBAR,  16)
    IRMD(DPTRAM4K, MISRH,   16)
    IRMD(DPTRAM4K, MISRL,   16)
    IRMD(DPTRAM4K, MISCNT,  16)
}
#endif

/*********************************************************************/
#ifdef CPU_MPC555
/*
 * The MPC555 has CMF_A and CMF_B Flash
 */
static void
irmd_cmf_a (char *reg, int regread, uint32 value)
{
    IRMD(CMF_A, CMFMCR, 32)
    IRMD(CMF_A, CMFTST, 32)
    IRMD(CMF_A, CMFCTL, 32)
}

static void
irmd_cmf_b (char *reg, int regread, uint32 value)
{
    IRMD(CMF_B, CMFMCR, 32)
    IRMD(CMF_B, CMFTST, 32)
    IRMD(CMF_B, CMFCTL, 32)
}
#endif

/*********************************************************************/
#if (defined (CPU_MPC563) || defined (CPU_MPC564) || \
     defined (CPU_MPC565) || defined (CPU_MPC566))
/*
 * The MPC563/4/5/6 have UC3F_A Flash
 */
static void
irmd_uc3f_a (char *reg, int regread, uint32 value)
{
    IRMD(UC3F_A, UC3FMCR,   32)
    IRMD(UC3F_A, UC3FMCRE,  32)
    IRMD(UC3F_A, UC3FCTL,   32)
}
#endif

/*********************************************************************/
#if (defined (CPU_MPC565) || defined (CPU_MPC566))
/*
 * The MPC565/6 have an additional Flash, UC3F_B
 */
static void
irmd_uc3f_b (char *reg, int regread, uint32 value)
{
    IRMD(UC3F_B, UC3FMCR,   32)
    IRMD(UC3F_B, UC3FMCRE,  32)
    IRMD(UC3F_B, UC3FCTL,   32)
}
#endif

/*********************************************************************/
#if (defined (CPU_MPC561) || defined (CPU_MPC562) || \
     defined (CPU_MPC563) || defined (CPU_MPC564))
/*
 * The MPC561/2/3/4 have a PPM
 */
static void
irmd_ppm (char *reg, int regread, uint32 value)
{
    IRMD(PPM, MCR,              16)
    IRMD(PPM, PCR,              16)
    IRMD(PPM, TX_CONFIG_1,      16)
    IRMD(PPM, TX_CONFIG_2,      16)
    IRMD(PPM, RX_CONFIG_1,      16)
    IRMD(PPM, RX_CONFIG_2,      16)
    IRMD(PPM, RX_DATA,          16)
    IRMD(PPM, RX_SHIFTER,       16)
    IRMD(PPM, TX_DATA,          16)
    IRMD(PPM, GPDO,             16)
    IRMD(PPM, GPDI,             16)
    IRMD(PPM, SHORT_REG,        16)
    IRMD(PPM, SHORT_CH_REG,     16)
    IRMD(PPM, SCALE_TCLK_REG,   16)
}
#endif

/*********************************************************************/
static const struct module_t
{
    char        *module;
    void        (*func)(char *, int, uint32);
} MODULE[] =
{
#if (defined (CPU_MPC555))
    {"USIU",        irmd_usiu},
    {"CMF_A",       irmd_cmf_a},
    {"CMF_B",       irmd_cmf_b},
    {"TPU_A",       irmd_tpu_a},
    {"TPU_B",       irmd_tpu_b},
    {"QADC_A",      irmd_qadc_a},
    {"QADC_B",      irmd_qadc_b},
    {"QSMCM",       irmd_qsmcm},
    {"MIOS1",       irmd_mios1},
    {"CAN_A",       irmd_can_a},
    {"CAN_B",       irmd_can_b},
    {"UIMB",        irmd_uimb},
    {"SRAM_A",      irmd_sram_a},
    {"SRAM_B",      irmd_sram_b},
    {"DPTRAM",      irmd_dptram},
#elif (defined (CPU_MPC561) || defined (CPU_MPC562))
    {"USIU",        irmd_usiu},
    {"TPU_A",       irmd_tpu_a},
    {"TPU_B",       irmd_tpu_b},
    {"QADC_A",      irmd_qadc_a},
    {"QADC_B",      irmd_qadc_b},
    {"QSMCM_A",     irmd_qsmcm_a},
    {"MIOS14",      irmd_mios14},
    {"CAN_A",       irmd_can_a},
    {"CAN_B",       irmd_can_b},
    {"CAN_C",       irmd_can_c},
    {"UIMB",        irmd_uimb},
    {"CALRAM_A",    irmd_calram_a},
    {"DPTRAM8K",    irmd_dptram8k},
    {"PPM",         irmd_ppm},
#elif (defined (CPU_MPC563) || defined (CPU_MPC564))
    {"USIU",        irmd_usiu},
    {"TPU_A",       irmd_tpu_a},
    {"TPU_B",       irmd_tpu_b},
    {"QADC_A",      irmd_qadc_a},
    {"QADC_B",      irmd_qadc_b},
    {"QSMCM_A",     irmd_qsmcm_a},
    {"MIOS14",      irmd_mios14},
    {"CAN_A",       irmd_can_a},
    {"CAN_B",       irmd_can_b},
    {"CAN_C",       irmd_can_c},
    {"UIMB",        irmd_uimb},
    {"CALRAM_A",    irmd_calram_a},
    {"DPTRAM8K",    irmd_dptram8k},
    {"PPM",         irmd_ppm},
    {"UC3F_A",      irmd_uc3f_a},
#elif (defined (CPU_MPC565) || defined (CPU_MPC566))
    {"USIU",        irmd_usiu},
    {"UC3F_A",      irmd_uc3f_a},
    {"UC3F_B",      irmd_uc3f_b},
    {"TPU_A",       irmd_tpu_a},
    {"TPU_B",       irmd_tpu_b},
    {"TPU_C",       irmd_tpu_c},
    {"QADC_A",      irmd_qadc_a},
    {"QADC_B",      irmd_qadc_b},
    {"QSMCM_A",     irmd_qsmcm_a},
    {"QSMCM_B",     irmd_qsmcm_b},
    {"MIOS14",      irmd_mios14},
    {"CAN_A",       irmd_can_a},
    {"CAN_B",       irmd_can_b},
    {"CAN_C",       irmd_can_c},
    {"UIMB",        irmd_uimb},
    {"CALRAM_A",    irmd_calram_a},
    {"CALRAM_B",    irmd_calram_b},
    {"DPTRAM6K",    irmd_dptram6k},
    {"DPTRAM4K",    irmd_dptram4k},
    {"DLCMD2",      irmd_dlcmd2},
#endif
} ;

#define MODULE_SIZE (int)(sizeof(MODULE)/sizeof(struct module_t))

/*************************************************/
void
mpc5xx_ird (int argc, char **argv)
{
    /*
     * Display Internal Memory Module contents.
     */
    //MPC5XX_IMMR *immr;
    char *rstr;
    char mstr[20];
    int mi;

    (void)argc;

    display_all = FALSE;
    displayed = 0;

    if (argv[1] == NULL)
    {
        printf("Internal Memory at %#08X", ISB_ADDRESS);
        for (mi = 0; mi < MODULE_SIZE; ++mi)
        {
            if ((mi % 8) == 0)
            {
                printf("\nModules: ");
            }
            printf("%s ",MODULE[mi].module);
        }
        printf("\n");
        return;
    };

    /*
     * Pick out module name and Point to register name
     */
    mi = 0;
    rstr = argv[1];
    while (*rstr != '.')
    {
        mstr[mi++] = *rstr;
        if (*++rstr == '\0')
        {
            rstr = NULL;
            break;
        }
    }
    mstr[mi] = '\0';
    if (*rstr == '.')
        ++rstr;

    /*
     * Display the module contents
     */
    for (mi = 0; mi < MODULE_SIZE; ++mi)
    {
        if (strcasecmp(MODULE[mi].module,mstr) == 0)
        {
            if (rstr == NULL)
            {
                display_all = TRUE;
                printf("Module: %s\n",MODULE[mi].module);
            }
            MODULE[mi].func(rstr, REGREAD, 0);
            return;
        }
    }

    printf(INVMOD,argv[1]);
}

/*********************************************************************/
void
mpc5xx_irm (int argc, char **argv)
{
    uint32 value;
    char *rstr;
    char mstr[20];
    int mi, success;

    (void)argc;

    display_all = FALSE;
    displayed = 0;

    /*
     * Pick out module name and Point to register name
     */
    mi = 0;
    rstr = argv[1];
    while (*rstr != '.')
    {
        mstr[mi++] = *rstr;
        if (*++rstr == '\0')
        {
            printf("Error:  Invalid Register:  %s\n",argv[1]);
            return;
        }
    }
    mstr[mi] = '\0';
    ++rstr;

    /*
     * Get the new value
     */
    value = get_value(argv[2],&success,16);
    if (success == 0)
    {
        printf(INVALUE,argv[2]);
        return;
    }

    /*
     * Determine which module
     */
    for (mi = 0; mi < MODULE_SIZE; ++mi)
    {
        if (strcasecmp(MODULE[mi].module,mstr) == 0)
        {
            MODULE[mi].func(rstr, REGWRITE, value);
            return;
        }
    }

    printf(INVMOD,argv[1]);
}

/*********************************************************************/
void
mpc5xx_call (int argc, char **argv)
{
    /*
     * This routine calls a subroutine from the command line
     * and returns control to dBUG upon return.
     */
    uint32 param;
    int index, success;

    param = get_value(argv[1],&success,BASE);
    if (success == 0)
    {
        printf(INVALUE,argv[1]);
        return;
    }
    CPU_REG_SRR0 = param;
    CPU_REG_LR = (uint32)&asm_return_from_call;

    for (index = 2; index < argc; ++index)
    {
        param = get_value(argv[index],&success,BASE);
        if (success == 0)
        {
            printf(INVALUE,argv[index]);
            return;
        }

        switch (index)
        {
            case 2:
                CPU_REG_R3 = param;
                break;
            case 3:
                CPU_REG_R4 = param;
                break;
            case 4:
                CPU_REG_R5 = param;
                break;
            case 5:
                CPU_REG_R6 = param;
                break;
            case 6:
                CPU_REG_R7 = param;
                break;
            case 7:
                CPU_REG_R8 = param;
                break;
            case 8:
                CPU_REG_R9 = param;
                break;
            case 9:
                CPU_REG_R10 = param;
                break;
            case 10:
                CPU_REG_R11 = param;
                break;
            default:
                break;
        }
    }
    cpu_switch_context(FALSE);
}

/*********************************************************************/
void
mpc5xx_rsr_display (void)
{
    #define MPC5XX_USIU_RSR_EHRS                (0x8000)
    #define MPC5XX_USIU_RSR_ESRS                (0x4000)
    #define MPC5XX_USIU_RSR_LLRS                (0x2000)
    #define MPC5XX_USIU_RSR_SWRS                (0x1000)
    #define MPC5XX_USIU_RSR_CSRS                (0x0800)
    #define MPC5XX_USIU_RSR_DBHRS               (0x0400)
    #define MPC5XX_USIU_RSR_DBSRS               (0x0200)
    #define MPC5XX_U