📄 mpc5xx_hi.c
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CPU_REG_MSR &= (~MPC_MSR_SE);
cpu_handler_flag = EXEC_DBUG;
cpu_trace_count = 0;
}
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x0E00:
printf(EXCEPT, exception, "Floating-Point Assist");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x0F00:
printf(EXCEPT, exception, "Reserved");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x1000:
if (!user_brkpnt)
{
printf(EXCEPT, exception, "Software Emulation");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
}
else
{
if ((ADDRESS)cpu_step_over == (ADDRESS)CPU_REG_SRR0)
{
/* clean up at end of handler */
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
}
if (user_triggered)
{
printf("Breakpoint encountered at %#08X\n",
CPU_REG_SRR0);
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
}
/* else reinstall breakpoints and continue */
/* execution of the task...we will return */
/* task from here, not write out regs and RFI */
else
{
if (breakpoint_install((ADDRESS)context.srr0))
{
/* about to execute at breakpoint */
/* trace thru rather than breaking */
trace_thru = CPU_REG_SRR0;
/* turn tracing on */
CPU_REG_MSR |= MPC_MSR_SE;
cpu_handler_flag = EXEC_RFI;
}
}
}
break;
case 0x1100:
printf(EXCEPT, exception, "Instruction TLB Miss");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x1200:
printf(EXCEPT, exception, "Data TLB Miss");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x1300:
printf(EXCEPT, exception, "Instruction TLB Error");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x1400:
printf(EXCEPT, exception, "Data TLB Error");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x1500:
case 0x1600:
case 0x1700:
case 0x1800:
case 0x1900:
case 0x1A00:
case 0x1B00:
printf(EXCEPT, exception, "Reserved");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x1C00:
printf(EXCEPT, exception, "Data Breakpoint");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x1D00:
printf(EXCEPT, exception, "Instruction Breakpoint");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
mpc5xx_wr_ictrl(mpc5xx_rd_ictrl() | 0x00000008);/*ignore next occurance of this breakpoint that got me here*/
break;
case 0x1E00:
printf(EXCEPT, exception, "Peripheral Breakpoint");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x1F00:
printf(EXCEPT, exception, "Development Port");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
case 0x0FF00: /* cheat for exit to dbug prompt */
cpu_handler_flag = EXEC_DBUG;
printf("\n");
break;
default:
printf(EXCEPT, exception, "Unknown");
cpu_reg_display(NULL);
cpu_disasm(CPU_REG_SRR0, TRUE);
break;
}
if ((cpu_handler_flag == EXEC_DBUG) && cpu_step_over)
{
cpu_step_over = 0;
}
return cpu_handler_flag;
}
/*********************************************************************/
void
cpu_cache_flush (void)
{
/*
* No cache in 5xx
*/
}
/*********************************************************************/
#define REGREAD (1)
#define REGWRITE (0)
static const char FORMAT8[] = " %8s: %02X\n";
static const char FORMAT16[] = " %8s: %04X\n";
static const char FORMAT32[] = " %8s: %08X\n";
#define IRMD(MOD,REG,SIZE) \
if ((strcasecmp(#REG,reg) == 0) || display_all) \
{ \
if (regread) \
{ \
printf(FORMAT ## SIZE, #REG, \
MOD . REG .R ); \
pause(&displayed); \
} \
else \
MOD . REG .R= (uint ## SIZE)value; \
\
if (!display_all) \
return; \
}
static int display_all;
static int displayed;
/*********************************************************************/
/*
* Common to all MPC5xx parts
*/
static void
irmd_usiu (char *reg, int regread, uint32 value)
{
IRMD(USIU, SIUMCR, 32)
IRMD(USIU, SYPCR, 32)
IRMD(USIU, SWSR, 16)
IRMD(USIU, SIPEND, 32)
IRMD(USIU, SIMASK, 32)
IRMD(USIU, SIEL, 32)
IRMD(USIU, SIVEC, 32)
IRMD(USIU, TESR, 32)
IRMD(USIU, SGPIODT1,32)
IRMD(USIU, SGPIODT2,32)
IRMD(USIU, SGPIOCR, 32)
IRMD(USIU, EMCR, 32)
IRMD(USIU, PDMCR, 32)
/*
* Only the MPC555 doesn't have these
*/
#ifndef CPU_MPC555
IRMD(USIU, PDMCR2, 32)
IRMD(USIU, SIPEND2, 32)
IRMD(USIU, SIPEND3, 32)
IRMD(USIU, SIMASK2, 32)
IRMD(USIU, SIMASK3, 32)
IRMD(USIU, SISR2, 32)
IRMD(USIU, SISR3, 32)
#endif
/*
* Memory Controller Registers
*/
IRMD(USIU, BR0, 32)
IRMD(USIU, OR0, 32)
IRMD(USIU, BR1, 32)
IRMD(USIU, OR1, 32)
IRMD(USIU, BR2, 32)
IRMD(USIU, OR2, 32)
IRMD(USIU, BR3, 32)
IRMD(USIU, OR3, 32)
IRMD(USIU, DMBR, 32)
IRMD(USIU, DMOR, 32)
IRMD(USIU, MSTAT, 16)
/*
* System integration Timers
*/
IRMD(USIU, TBSCR, 16)
IRMD(USIU, TBREF0, 32)
IRMD(USIU, TBREF1, 32)
IRMD(USIU, RTCSC, 16)
IRMD(USIU, RTC, 32)
IRMD(USIU, RTSEC, 32)
IRMD(USIU, RTCAL, 32)
IRMD(USIU, PISCR, 16)
IRMD(USIU, PITC, 32)
IRMD(USIU, PITR, 32)
/*
* Clocks and Reset
*/
IRMD(USIU, SCCR, 32)
IRMD(USIU, PLPRCR, 32)
IRMD(USIU, RSR, 16)
IRMD(USIU, COLIR, 16)
IRMD(USIU, VSRMCR, 16)
/*
* System Integration Timer Keys
*/
/* IRMD(USIU, TBSCRK, 32)
IRMD(USIU, TBREF0K, 32)
IRMD(USIU, TBREF1K, 32)
IRMD(USIU, TBK, 32)
IRMD(USIU, RTCSCK, 32)
IRMD(USIU, RTCK, 32)
IRMD(USIU, RTSECK, 32)
IRMD(USIU, RTCALK, 32)
IRMD(USIU, PISCRK, 32)
IRMD(USIU, PITCK, 32)
*/ /*will lock if you read these registers*/
/*
* Clocks and Reset Keys
*/
/* IRMD(USIU, SCCRK, 32)
IRMD(USIU, PLPRCRK, 32)
IRMD(USIU, RSRK, 16)
*/ /*will lock if you read these registers*/
}
/****************************************************************************/
#ifdef CPU_MPC555
/*
* Only the MPC555 has SRAM_A and SRAM_B
*/
static void
irmd_sram_a (char *reg, int regread, uint32 value)
{
IRMD(SRAM_A, SRAMMCR, 32)
IRMD(SRAM_A, SRAMTST, 32)
}
/****************************************************************************/
static void
irmd_sram_b (char *reg, int regread, uint32 value)
{
IRMD(SRAM_B, SRAMMCR, 32)
IRMD(SRAM_B, SRAMTST, 32)
}
#endif
/****************************************************************************/
#ifndef CPU_MPC555
/*
* All parts except MPC555 have CALRAM_A
*/
static void
irmd_calram_a (char *reg, int regread, uint32 value)
{
IRMD(CALRAM_A, CRAMMCR, 32)
IRMD(CALRAM_A, CRAMTST, 32)
IRMD(CALRAM_A, CRAM_RBA0, 32)
IRMD(CALRAM_A, CRAM_RBA1, 32)
IRMD(CALRAM_A, CRAM_RBA2, 32)
IRMD(CALRAM_A, CRAM_RBA3, 32)
IRMD(CALRAM_A, CRAM_RBA4, 32)
IRMD(CALRAM_A, CRAM_RBA5, 32)
IRMD(CALRAM_A, CRAM_RBA6, 32)
IRMD(CALRAM_A, CRAM_RBA7, 32)
IRMD(CALRAM_A, CRAMOTR, 32)
}
#endif
/****************************************************************************/
#if (defined(CPU_MPC565) || defined (CPU_MPC566))
/*
* Only the MPC565/6 have CALRAM_B
*/
static void
irmd_calram_b (char *reg, int regread, uint32 value)
{
IRMD(CALRAM_B, CRAMMCR, 32)
IRMD(CALRAM_B, CRAMTST, 32)
IRMD(CALRAM_B, CRAM_RBA0, 32)
IRMD(CALRAM_B, CRAM_RBA1, 32)
IRMD(CALRAM_B, CRAM_RBA2, 32)
IRMD(CALRAM_B, CRAM_RBA3, 32)
IRMD(CALRAM_B, CRAM_RBA4, 32)
IRMD(CALRAM_B, CRAM_RBA5, 32)
IRMD(CALRAM_B, CRAM_RBA6, 32)
IRMD(CALRAM_B, CRAM_RBA7, 32)
IRMD(CALRAM_B, CRAMOTR, 32)
}
#endif
/****************************************************************************/
/*
* Common to all MPC5xx parts
*/
static void
irmd_uimb (char *reg, int regread, uint32 value)
{
IRMD(UIMB, UMCR, 32)
IRMD(UIMB, UTSTCREG, 32)
IRMD(UIMB, UIPEND, 32)
}
/****************************************************************************/
/*
* Common to all MPC5xx parts
*/
static void
irmd_tpu_a (char *reg, int regread, uint32 value)
{
IRMD(TPU_A, TPUMCR, 16)
IRMD(TPU_A, TICR, 16)
IRMD(TPU_A, CIER, 16)
IRMD(TPU_A, CFSR0, 16)
IRMD(TPU_A, CFSR1, 16)
IRMD(TPU_A, CFSR2, 16)
IRMD(TPU_A, CFSR3, 16)
IRMD(TPU_A, HSQR0, 16)
IRMD(TPU_A, HSQR1, 16)
IRMD(TPU_A, HSRR0, 16)
IRMD(TPU_A, HSRR1, 16)
IRMD(TPU_A, CPR0, 16)
IRMD(TPU_A, CPR1, 16)
IRMD(TPU_A, CISR, 16)
IRMD(TPU_A, TPUMCR2,16)
IRMD(TPU_A, TPUMCR3,16)
}
/****************************************************************************/
/*
* Common to all MPC5xx parts
*/
static void
irmd_tpu_b (char *reg, int regread, uint32 value)
{
IRMD(TPU_B, TPUMCR, 16)
IRMD(TPU_B, TICR, 16)
IRMD(TPU_B, CIER, 16)
IRMD(TPU_B, CFSR0, 16)
IRMD(TPU_B, CFSR1, 16)
IRMD(TPU_B, CFSR2, 16)
IRMD(TPU_B, CFSR3, 16)
IRMD(TPU_B, HSQR0, 16)
IRMD(TPU_B, HSQR1, 16)
IRMD(TPU_B, HSRR0, 16)
IRMD(TPU_B, HSRR1, 16)
IRMD(TPU_B, CPR0, 16)
IRMD(TPU_B, CPR1, 16)
IRMD(TPU_B, CISR, 16)
IRMD(TPU_B, TPUMCR2,16)
IRMD(TPU_B, TPUMCR3,16)
}
/****************************************************************************/
#if (defined (CPU_MPC565) || defined (CPU_MPC566))
/*
* Only the MPC565/6 have TPU3_C
*/
static void
irmd_tpu_c (char *reg, int regread, uint32 value)
{
IRMD(TPU_C, TPUMCR, 16)
IRMD(TPU_C, TICR, 16)
IRMD(TPU_C, CIER, 16)
IRMD(TPU_C, CFSR0, 16)
IRMD(TPU_C, CFSR1, 16)
IRMD(TPU_C, CFSR2, 16)
IRMD(TPU_C, CFSR3, 16)
IRMD(TPU_C, HSQR0, 16)
IRMD(TPU_C, HSQR1, 16)
IRMD(TPU_C, HSRR0, 16)
IRMD(TPU_C, HSRR1, 16)
IRMD(TPU_C, CPR0, 16)
IRMD(TPU_C, CPR1, 16)
IRMD(TPU_C, CISR, 16)
IRMD(TPU_C, TPUMCR2,16)
IRMD(TPU_C, TPUMCR3,16)
}
#endif
/****************************************************************************/
static void
/*
* Common to all MPC5xx parts
*/
irmd_can_a (char *reg, int regread, uint32 value)
{
IRMD(CAN_A, TCNMCR, 16)
IRMD(CAN_A, CANICR, 16)
IRMD(CAN_A, CANCTRL0, 8)
IRMD(CAN_A, CANCTRL1, 8)
IRMD(CAN_A, PRESDIV, 8)
IRMD(CAN_A, CANCTRL2, 8)
IRMD(CAN_A, TIMER, 16)
IRMD(CAN_A, RXGMSKHI, 16)
IRMD(CAN_A, RXGMSKLO, 16)
IRMD(CAN_A, RX14MSKHI, 16)
IRMD(CAN_A, RX14MSKLO, 16)
IRMD(CAN_A, RX15MSKHI, 16)
IRMD(CAN_A, RX15MSKLO, 16)
IRMD(CAN_A, ESTAT, 16)
IRMD(CAN_A, IMASK, 16)
IRMD(CAN_A, IFLAG, 16)
IRMD(CAN_A, RXECTR, 8)
IRMD(CAN_A, TXECTR, 8)
}
/****************************************************************************/
/*
* Common to all MPC5xx parts
*/
static void
irmd_can_b (char *reg, int regread, uint32 value)
{
IRMD(CAN_B, TCNMCR, 16)
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