📄 mpc5xx_lo.s
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# Save volatile registers, as per EABI
#
stwu r1,-ISRSZ(r1)
stw r0,40(r1) # Save R0
stw r2,44(r1) # Save R2
stw r3,48(r1) # Save R3
stw r4,52(r1) # Save R4
stw r5,56(r1) # Save R5
stw r6,60(r1) # Save R6
stw r7,64(r1) # Save R7
stw r8,68(r1) # Save R8
stw r9,72(r1) # Save R9
stw r10,76(r1) # Save R10
stw r11,80(r1) # Save R11
stw r12,84(r1) # Save R12
stw r13,88(r1) # Save R13
mfspr r0,spr_sprg1
stw r0,92(r1) # Save LR - Exception header
mfcr r0
stw r0,96(r1) # Save CR
mfspr r0,spr_xer
stw r0,100(r1) # Save XER
mfspr r0,spr_ctr
stw r0,104(r1) # Save CTR
mfspr r0,spr_sprg0
stw r0,108(r1) # Save R31 - Exception header
mfspr r0,spr_srr0
stw r0,112(r1) # Save IP
mfspr r0,spr_srr1
stw r0,116(r1) # Save MSR
sync
isync
# Call the higher level interrupt handler
#
mfspr r4,8 # LR contains exception number
addis r5,r0,(EMASK)@h # Get exception number
ori r5,r5,(EMASK)@l
and r3,r4,r5
bl isr_execute_handler
# Code to determine if we go back to monitor or user code
# r3 == 0 if IRQ not handled, r3 == 1 if IRQ handled
cmpi cr0,0,r3,0x0000
beq cr0,nothandled
handled:
# Restore registers
#
lwz r2,44(r1) # Restore R2
lwz r3,48(r1) # Restore R3
lwz r4,52(r1) # Restore R4
lwz r5,56(r1) # Restore R5
lwz r6,60(r1) # Restore R6
lwz r7,64(r1) # Restore R7
lwz r8,68(r1) # Restore R8
lwz r9,72(r1) # Restore R9
lwz r10,76(r1) # Restore R10
lwz r11,80(r1) # Restore R11
lwz r12,84(r1) # Restore R12
lwz r13,88(r1) # Restore R13
lwz r0,92(r1) #
mtspr spr_lr,r0 # Restore LR
lwz r0,96(r1) #
mtcrf 0xFF,r0 # Restore CR
lwz r0,100(r1) #
mtspr spr_xer,r0 # Restore XER
lwz r0,104(r1) #
mtspr spr_ctr,r0 # Restore CTR
lwz r31,108(r1) # Restore R31
lwz r0,112(r1)
mtspr spr_srr0,r0 # Restore IP
lwz r0,116(r1)
mtspr spr_srr1,r0 # Restore MSR
lwz r0,40(r1) # Restore R0 - Must be done last!
addi r1,r1,ISRSZ
sync
isync
# All done!
rfi
nothandled:
# Restore registers
#
lwz r2,44(r1) # Restore R2
lwz r3,48(r1) # Restore R3
lwz r4,52(r1) # Restore R4
lwz r5,56(r1) # Restore R5
lwz r6,60(r1) # Restore R6
lwz r7,64(r1) # Restore R7
lwz r8,68(r1) # Restore R8
lwz r9,72(r1) # Restore R9
lwz r10,76(r1) # Restore R10
lwz r11,80(r1) # Restore R11
lwz r12,84(r1) # Restore R12
lwz r13,88(r1) # Restore R13
lwz r0,92(r1) #
mtspr spr_sprg1,r0 # Restore LR (for exception body)
lwz r0,96(r1) #
mtcrf 0xFF,r0 # Restore CR
lwz r0,100(r1) #
mtspr spr_xer,r0 # Restore XER
lwz r0,104(r1) #
mtspr spr_ctr,r0 # Restore CTR
lwz r31,108(r1) # Restore R31
mtspr spr_sprg0,r31 # Restore r31 (for exception body)
lwz r0,112(r1)
mtspr spr_srr0,r0 # Restore IP
lwz r0,116(r1)
mtspr spr_srr1,r0 # Restore MSR
lwz r0,40(r1) # Restore R0 - Must be done last!
addi r1,r1,ISRSZ
sync
isync
# Jump to generic exception handler
addi r31,r0,0x0500
mtspr spr_lr,r31
b asm_exception_body
######################################################################
#
# These routines perform I/O to memory mapped I/O peripherals.
#
# uint32 cpu_iord_8 (void *addr);
# uint32 cpu_iord_16(void *addr);
# uint32 cpu_iord_32(void *addr);
# void cpu_iowr_8 (void *addr, uint32 data);
# void cpu_iowr_16(void *addr, uint32 data);
# void cpu_iowr_32(void *addr, uint32 data);
#
# Under EABI, addr is in r3, and data is in r4. Return value also in r3
#
cpu_iord_8:
eieio
lbz r3,0(r3)
eieio
blr
cpu_iord_16:
eieio
lhz r3,0(r3)
eieio
blr
cpu_iord_32:
eieio
lwz r3,0(r3)
eieio
blr
cpu_iowr_8:
eieio
stb r4,0(r3)
eieio
blr
cpu_iowr_16:
eieio
sth r4,0(r3)
eieio
blr
cpu_iowr_32:
eieio
stw r4,0(r3)
eieio
blr
######################################################################
#
# These routines read and write the value of the Machine State Register
# MSR.
#
mpc5xx_wr_msr:
isync
mtmsr r3
isync
blr
mpc5xx_rd_msr:
mfmsr r3
isync
blr
#
# These routines read and write the value of the Special Purpose Register
# 144, CMPA.
#
mpc5xx_wr_cmpa:
isync
mtspr 144,r3
isync
blr
mpc5xx_rd_cmpa:
mfspr r3,144
isync
blr
#
# These routines read and write the value of the Special Purpose Register
# 145, CMPB.
#
mpc5xx_wr_cmpb:
isync
mtspr 145,r3
isync
blr
mpc5xx_rd_cmpb:
mfspr r3,145
isync
blr
#
# These routines read and write the value of the Special Purpose Register
# 146, CMPC.
#
mpc5xx_wr_cmpc:
isync
mtspr 146,r3
isync
blr
mpc5xx_rd_cmpc:
mfspr r3,146
isync
blr
#
# These routines read and write the value of the Special Purpose Register
# 147, CMPD.
#
mpc5xx_wr_cmpd:
isync
mtspr 147,r3
isync
blr
mpc5xx_rd_cmpd:
mfspr r3,147
isync
blr
#
# These routines read and write the value of the Debug Enable Register
# .
#
mpc5xx_wr_der:
isync
mtspr 149,r3
isync
blr
mpc5xx_rd_der:
mfspr r3,149
isync
blr
#
# These routines read and write the value of the I-bus Control Register
# ICTRL.
#
mpc5xx_wr_ictrl:
isync
mtspr 158,r3
isync
blr
mpc5xx_rd_ictrl:
mfspr r3,158
isync
blr
#
# These routines read and write the value of the Lower TimeBase
#
mpc5xx_rd_tbl:
mftb r3,268
blr
mpc5xx_wr_tbl:
mtspr 284,r3
isync
blr
#
# These routines read and write the value of the Upper TimeBase
#
mpc5xx_rd_tbu:
mftb r3,269
blr
mpc5xx_wr_tbu:
mtspr 285,r3
isync
blr
#
# Debug Port Interrupt Cause Register, ICR
#
mpc5xx_rd_ecr:
mfspr r3,spr_5xx_ecr
blr
#
# These routines read and write the value of the DECrementer
#
mpc5xx_wr_dec:
mtspr spr_dec,r3
isync
blr
mpc5xx_rd_dec:
isync
mfspr r3,spr_dec
blr
#
# These routines are used to read and write the value of the IMMR, the
# MPC5xx Internal Memory Map Register. This register provides an
# address base and 64K "wide" space for accessing the on-board
# peripherals.
#
mpc5xx_wr_immr:
###rlwinm r3,r3,0,0,15 # mask out lower 16 bits
rlwinm r3,r3,0,16,31 #mask out upper 16 bits
mtspr spr_5xx_immr,r3
blr
mpc5xx_rd_immr:
mfspr r3,spr_5xx_immr
blr
mpc5xx_get_immp:
mfspr r3,spr_5xx_immr
rlwinm r3,r3,21,6,10 # mask out the upper 27 bits and mask out bit 31. then shift left 21 bits to go with table on pg.6-23 of 565 manual.
rlwinm r3,r3,0,0,30 #mask out bit 31 (LSB)
###rlwinm r3,r3,0,0,15 # mask out lower 16 bits
blr
.end
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