📄 mpc5xx_lo.s
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lis r3,(main)@h
ori r3,r3,(main)@l
mtspr spr_lr,r3
bclrl 20,0 # branch to C main()
######################################################################
#
# When this function is invoked from the exception handler headers
# above, the following is true:
#
# sprg0 == r31
# sprg1 == LR
# LR[16-23] == exception number
#
# This routine then saves the entire context and invokes the C
# exception handler.
#
.equ MSR_E_MASK,0x87C0FFFF
asm_exception_body:
# Point r31 to the user register data structure
addis r31,r0,(context)@h
ori r31,r31,(context)@l
# Store all GPRs.
stw r0,o_r0(r31) # store r0
stw r1,o_r1(r31) # store r1
stw r2,o_r2(r31) # store r2
stw r3,o_r3(r31) # store r3
stw r4,o_r4(r31) # store r4
stw r5,o_r5(r31) # store r5
stw r6,o_r6(r31) # store r6
stw r7,o_r7(r31) # store r7
stw r8,o_r8(r31) # store r8
stw r9,o_r9(r31) # store r9
stw r10,o_r10(r31) # store r10
stw r11,o_r11(r31) # store r11
stw r12,o_r12(r31) # store r12
stw r13,o_r13(r31) # store r13
stw r14,o_r14(r31) # store r14
stw r15,o_r15(r31) # store r15
stw r16,o_r16(r31) # store r16
stw r17,o_r17(r31) # store r17
stw r18,o_r18(r31) # store r18
stw r19,o_r19(r31) # store r19
stw r20,o_r20(r31) # store r20
stw r21,o_r21(r31) # store r21
stw r22,o_r22(r31) # store r22
stw r23,o_r23(r31) # store r23
stw r24,o_r24(r31) # store r24
stw r25,o_r25(r31) # store r25
stw r26,o_r26(r31) # store r26
stw r27,o_r27(r31) # store r27
stw r28,o_r28(r31) # store r28
stw r29,o_r29(r31) # store r29
stw r30,o_r30(r31) # store r30
# Do r31 now. R31 in sprg0.
mfspr r10,spr_sprg0
stw r10,o_r31(r31) # store r31
sync
# Zero r0
addi r0,0,0
# Reconstruct MSR
addis r10,r0,(MSR_E_MASK)@h
ori r10,r10,(MSR_E_MASK)@l
mfspr r11,spr_srr1
and r11,r10,r11
addis r12,r0,(~MSR_E_MASK)@h
ori r12,r12,(~MSR_E_MASK)@l
mfmsr r13
isync
and r13,r12,r13
or r10,r11,r13
# Save MSR, CR, IP, XER, LR, CTR
mfcr r11
mfspr r12,spr_srr0
mfspr r13,spr_xer
mfspr r14,spr_sprg1 # LR from asm_exception_head
mfspr r15,spr_ctr
stw r10,o_msr(r31)
stw r11,o_cr(r31)
stw r12,o_srr0(r31)
stw r13,o_xer(r31)
stw r14,o_lr(r31)
stw r15,o_ctr(r31)
sync
# Save LR before calling routines (LR contains exception number)
# (Once LR saved, it is okay to use subroutine calls)
#
mfspr r30,spr_lr
mtspr spr_sprg1,r30 # LR from bl in asm_exception_head
#
# Change the MSR to suit the needs of the debugger.
# No interrupts, tracing, address or data translations.
#
.equ DBUG_MSR,0x00001042
addis r30,r0,(DBUG_MSR)@h
ori r30,r30,(DBUG_MSR)@l
mtmsr r30
isync
#
# Store the Special Purpose Registers
#
tbloop:
mftb r14,269 # TBU
mftb r13,268 # TBL
mftb r15,269 # TBU
cmpw r15,r14
bne tbloop
mfspr r15,spr_pvr
stw r13,o_tbl(r31)
stw r14,o_tbu(r31)
stw r15,o_pvr(r31)
sync
mfspr r13,spr_dsisr
mfspr r14,spr_dar
mfspr r15,spr_dec
mfspr r16,spr_5xx_immr
stw r13,o_dsisr(r31)
stw r14,o_dar(r31)
stw r15,o_dec(r31)
stw r16,o_5xx_immr(r31)
sync
#mfspr r10,spr_5xx_ic_cst
#mfspr r11,spr_5xx_ic_adr
#mfspr r12,spr_5xx_ic_dat
#mfspr r13,spr_5xx_dc_cst
#mfspr r14,spr_5xx_dc_adr
#mfspr r15,spr_5xx_dc_dat
#mfspr r16,spr_5xx_mi_ctr
#mfspr r17,spr_5xx_mi_ap
#mfspr r18,spr_5xx_mi_epn
#mfspr r19,spr_5xx_mi_twc
#mfspr r20,spr_5xx_mi_rpn
#mfspr r21,spr_5xx_mi_dbcam
#mfspr r22,spr_5xx_mi_dbram0
#mfspr r23,spr_5xx_mi_dbram1
#stw r10,o_5xx_ic_cst(r31)
#stw r11,o_5xx_ic_adr(r31)
#stw r12,o_5xx_ic_dat(r31)
#stw r13,o_5xx_dc_cst(r31)
#stw r14,o_5xx_dc_adr(r31)
#stw r15,o_5xx_dc_dat(r31)
#stw r16,o_5xx_mi_ctr(r31)
#stw r17,o_5xx_mi_ap(r31)
#stw r18,o_5xx_mi_epn(r31)
#stw r19,o_5xx_mi_twc(r31)
#stw r20,o_5xx_mi_rpn(r31)
#stw r21,o_5xx_mi_dbcam(r31)
#stw r22,o_5xx_mi_dbram0(r31)
#stw r23,o_5xx_mi_dbram1(r31)
sync
#mfspr r10,spr_5xx_md_ctr
#mfspr r11,spr_5xx_m_casid
#mfspr r12,spr_5xx_md_ap
#mfspr r13,spr_5xx_md_epn
#mfspr r14,spr_5xx_m_twb
#mfspr r15,spr_5xx_md_twc
#mfspr r16,spr_5xx_md_rpn
#mfspr r17,spr_5xx_m_tw
#mfspr r18,spr_5xx_md_dbcam
#mfspr r19,spr_5xx_md_dbram0
#mfspr r20,spr_5xx_md_dbram1
#stw r10,o_5xx_md_ctr(r31)
#stw r11,o_5xx_m_casid(r31)
#stw r12,o_5xx_md_ap(r31)
#stw r13,o_5xx_md_epn(r31)
#stw r14,o_5xx_m_twb(r31)
#stw r15,o_5xx_md_twc(r31)
#stw r16,o_5xx_md_rpn(r31)
#stw r17,o_5xx_m_tw(r31)
#stw r18,o_5xx_md_dbcam(r31)
#stw r19,o_5xx_md_dbram0(r31)
#stw r20,o_5xx_md_dbram1(r31)
sync
#
# Context save complete!
#
# Change to the monitor stack.
#
addis r1,r0,(__SP_INIT-20)@h
ori r1,r1,(__SP_INIT-20)@l
# Invoke the C exception handler.
#
# int cpu_handler (int exception);
#
mfspr r3,spr_sprg1 # the address in LR indicates exception
bl cpu_handler
# Code to determine if we go back to monitor or user code
# r3 == 1 if we go back to monitor, 0 for RFI
cmpi cr0,0,r3,0x0001
beq cr0,backtomonitor
# restore state and execute rfi.
# Point r3 to the user register data structure
addis r3,r0,(context)@h
ori r3,r3,(context)@l
b asm_switch_context
# The RFI is performed in asm_switch_context
backtomonitor:
# mask exceptions -- FIX
b mainloop
######################################################################
# This routine accepts a pointer to the data structure containing
# the user register set, and restores its context.
# Call from C:
#
# asm_switch_context(&context);
#
# NOTE: This routine only restores SPRs 1, 8, 9, 275, and 1010
#
asm_switch_context:
# Point r31 to the user register data structure
addi r31,r3,0 # arg in r3
# Special Purpose Registers
lwz r10,o_xer(r31)
lwz r11,o_lr(r31)
lwz r12,o_ctr(r31)
lwz r13,o_dsisr(r31)
lwz r14,o_dar(r31)
lwz r15,o_dec(r31)
mtspr spr_xer,r10
mtspr spr_lr,r11
mtspr spr_ctr,r12
# mtspr spr_dsisr,r13
# mtspr spr_dar,r14
# mtspr spr_dec,r15
sync
# Some of the MMU registers could be done here! FIX !!!
# Restore CR, and setup MSR, IP for the RFI
lwz r10,o_cr(r31)
lwz r11,o_msr(r31)
lwz r12,o_srr0(r31)
mtcrf 0xFF,r10
mtspr spr_srr1,r11
mtspr spr_srr0,r12
sync
# Restore all GPRs.
lwz r0,o_r0(r31)
lwz r1,o_r1(r31)
lwz r2,o_r2(r31)
lwz r3,o_r3(r31)
lwz r4,o_r4(r31)
lwz r5,o_r5(r31)
lwz r6,o_r6(r31)
lwz r7,o_r7(r31)
lwz r8,o_r8(r31)
lwz r9,o_r9(r31)
lwz r10,o_r10(r31)
lwz r11,o_r11(r31)
lwz r12,o_r12(r31)
lwz r13,o_r13(r31)
lwz r14,o_r14(r31)
lwz r15,o_r15(r31)
lwz r16,o_r16(r31)
lwz r17,o_r17(r31)
lwz r18,o_r18(r31)
lwz r19,o_r19(r31)
lwz r20,o_r20(r31)
lwz r21,o_r21(r31)
lwz r22,o_r22(r31)
lwz r23,o_r23(r31)
lwz r24,o_r24(r31)
lwz r25,o_r25(r31)
lwz r26,o_r26(r31)
lwz r27,o_r27(r31)
lwz r28,o_r28(r31)
lwz r29,o_r29(r31)
lwz r30,o_r30(r31)
lwz r31,o_r31(r31) # must be done last
sync
isync
# Here we go!
rfi
######################################################################
#
# This routine is used to return from a 'call' command. It uses
# asm_sc_exit_to_dbug as well. Since a return from a call has no
# real IP, we dummy it up.
#
asm_return_from_call:
mtspr spr_sprg1,r31
mfmsr r31
mtspr spr_srr1,r31
mfspr r31,spr_lr
mtspr spr_srr0,r31
mfspr r31,spr_sprg1
# we now let the following routine finish it off
######################################################################
#
# This routine is called from a system call to save the context and
# return to the dBUG prompt. This routine is used in conjuction with
# asm_exception_body() and cpu_handler() to avoid rewriting/copying
# the context save code. It passes exception #0xFF00 to cpu_handler(),
# which will then dump out to the dBUG prompt.
#
# Prior to invoking this routine, the caller must have ensured that
# the entry conditions for asm_exception_body have already been met,
# with the exception that LR is set here to indicate bogus exception.
#
asm_sc_exit_to_dbug:
addi r31,0,-1
mtspr spr_lr,r31
b asm_exception_body
######################################################################
#
# This is the Interrupt Service Routine for External Interrupts. This
# routine saves off a few registers that may be modified ala EABI, and
# then calls the higher level C routine to determine and dispatch the
# correct interrupt handler.
#
.equ ISRSZ,128
.equ EMASK,0x0000FF00
asm_isr_handler:
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