mpc5xx_lo.s

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

    ######################################################################
    # File:     mpc5xx_lo.s
    #
    # Purpose:  Lowest level routines for all MPC5XX dBUG (modified from mpc8xx_lo.s)
    #
    # Notes:    This file assembles with both Diab and GNU assemblers
    #
    # Last Updated: 
    #
    # Modificiations: 
    #
    #######################################################################

    # Globally accessible symbols
    .extern VECTOR_TABLE
    .extern __ISB
    .extern mpc5xx_init

    .global asm_startmeup           # Called by dBUG RESET command
    .global asm_exception_body
    .global asm_isr_handler
    .global asm_switch_context
    .global asm_sc_exit_to_dbug
    .global asm_return_from_call

    .global cpu_iord_8
    .global cpu_iord_16
    .global cpu_iord_32
    .global cpu_iowr_8
    .global cpu_iowr_16
    .global cpu_iowr_32

    .global mpc5xx_wr_msr
    .global mpc5xx_rd_msr
    
    .global mpc5xx_wr_cmpa
    .global mpc5xx_rd_cmpa
    
    .global mpc5xx_wr_cmpb
    .global mpc5xx_rd_cmpb

    .global mpc5xx_wr_cmpc
    .global mpc5xx_rd_cmpc

    .global mpc5xx_wr_cmpd
    .global mpc5xx_rd_cmpd
        
    .global mpc5xx_wr_der
    .global mpc5xx_rd_der

    .global mpc5xx_wr_dec
    .global mpc5xx_rd_dec

    .global mpc5xx_rd_tbl
    .global mpc5xx_wr_tbl
    .global mpc5xx_rd_tbu
    .global mpc5xx_wr_tbu

    .global mpc5xx_rd_icr

    .global mpc5xx_rd_ictrl
    .global mpc5xx_wr_ictrl

    .global mpc5xx_wr_immr
    .global mpc5xx_rd_immr
    .global mpc5xx_get_immp

######################################################################

    #
    # Offsets of registers in the REGISTERS data structure.
    # NOTE:  Offsets must match those in dbug\src\cpu\ppc\mpc5xx\mpc5xx.h
    #

    .equ    o_r0,0
    .equ    o_r1,4
    .equ    o_r2,8
    .equ    o_r3,12
    .equ    o_r4,16
    .equ    o_r5,20
    .equ    o_r6,24
    .equ    o_r7,28
    .equ    o_r8,32
    .equ    o_r9,36
    .equ    o_r10,40
    .equ    o_r11,44
    .equ    o_r12,48
    .equ    o_r13,52
    .equ    o_r14,56
    .equ    o_r15,60
    .equ    o_r16,64
    .equ    o_r17,68
    .equ    o_r18,72
    .equ    o_r19,76
    .equ    o_r20,80
    .equ    o_r21,84
    .equ    o_r22,88
    .equ    o_r23,92
    .equ    o_r24,96
    .equ    o_r25,100
    .equ    o_r26,104
    .equ    o_r27,108
    .equ    o_r28,112
    .equ    o_r29,116
    .equ    o_r30,120
    .equ    o_r31,124
    .equ    o_cr,132                #condition register
    .equ    o_msr,128               #machine state register
    .equ    o_xer,136               #integer exception register
    .equ    o_lr,140                #link register
    .equ    o_ctr,144               #count register
    .equ    o_dsisr,148             #DAE/Source Instruction Service Register
    .equ    o_dar,152               #data address register
    .equ    o_dec,156               #decrementer register
    .equ    o_srr0,160              #machine status save/restore register 0
    .equ    o_srr1,164              #machine status save/restore register 0
    .equ    o_tbl,172               #time base lower (SPR268 for reading)
    .equ    o_tbu,176               #time base upper (SPR269 for reading)
    .equ    o_sprg0,180             #general SPR 0 (special purpose register)
    .equ    o_sprg1,184             #general SPR 1 (special purpose register)
    .equ    o_sprg2,188             #general SPR 2 (special purpose register)
    .equ    o_sprg3,192             #general SPR 3 (special purpose register)
    .equ    o_pvr,168               #processor version register
    .equ    o_5xx_eie,196           #(implementation specific SPR - see 3.9.10.1)
    .equ    o_5xx_eid,200           #(implementation specific SPR - see 3.9.10.1)
    .equ    o_5xx_nri,204           #(implementation specific SPR - see 3.9.10.1)
    .equ    o_5xx_cmpa,208          #comparator A value register
    .equ    o_5xx_cmpb,212          #comparator B value register
    .equ    o_5xx_cmpc,216          #comparator C value register
    .equ    o_5xx_cmpd,220          #comparator D value register
    .equ    o_5xx_ecr,224           #Exception Cause Register
    .equ    o_5xx_der,228           #debug enable register
    .equ    o_5xx_counta,232        #breakpoint counter A value and control
    .equ    o_5xx_countb,236        #breakpoint counter B value and control
    .equ    o_5xx_cmpe,240          #comparator E value register
    .equ    o_5xx_cmpf,244          #comparator F value register
    .equ    o_5xx_cmpg,248          #comparator G value register
    .equ    o_5xx_cmph,252          #comparator H value register
    .equ    o_5xx_lctrl1,256            #L-bus support comparators control 1
    .equ    o_5xx_lctrl2,260            #L-bus support comparators control 2
    .equ    o_5xx_ictrl,264         #I-bus support control register
    .equ    o_5xx_bar,268           #breakpoint address register
    .equ    o_5xx_dpdr,280          #development port data register
    .equ    o_5xx_immr,284          # ???
    .equ    o_5xx_fpscr,492         #Floating Point Satus and Control Register
    .equ    o_5xx_mi_gra,272            #Global Region Attribute Register
    .equ    o_5xx_l2u_gra,276           #L2U Global Region Attribute Register
    .equ    o_5xx_bbcmcr,288            #BBC Module Configuration Register
    .equ    o_5xx_l2u_mcr,292           #L2U Module Configuration Register
    .equ    o_5xx_mi_rba0,296           #Region Address Register 0
    .equ    o_5xx_mi_rba1,300           #Region Address Register 1
    .equ    o_5xx_mi_rba2,304           #Region Address Register 2
    .equ    o_5xx_mi_rba3,308           #Region Address Register 3
    .equ    o_5xx_mi_ra0,312            #Region Attribute Register 0
    .equ    o_5xx_mi_ra1,316            #Region Attribute Register 1
    .equ    o_5xx_mi_ra2,320            #Region Attribute Register 2
    .equ    o_5xx_mi_ra3,324            #Region Attribute Register 3
    .equ    o_5xx_l2u_rba0,328          #L2U Region 0 Address Register
    .equ    o_5xx_l2u_rba1,332          #L2U Region 1 Address Register
    .equ    o_5xx_l2u_rba2,336          #L2U Region 2 Address Register
    .equ    o_5xx_l2u_rba3,340          #L2U Region 3 Address Register
    .equ    o_5xx_l2u_ra0,344           #L2U Region 0 Attribute Register
    .equ    o_5xx_l2u_ra1,348           #L2U Region 1 Attribute Register
    .equ    o_5xx_l2u_ra2,352           #L2U Region 2 Attribute Register
    .equ    o_5xx_l2u_ra3,356           #L2U Region 3 Attribute Register
    .equ    o_5xx_fpecr,360
    
    .equ    o_5xx_fpr0,364          #Floating Point Registers:
    .equ    o_5xx_fpr1,368
    .equ    o_5xx_fpr2,372
    .equ    o_5xx_fpr3,376
    .equ    o_5xx_fpr4,380
    .equ    o_5xx_fpr5,384
    .equ    o_5xx_fpr6,388
    .equ    o_5xx_fpr7,392
    .equ    o_5xx_fpr8,396
    .equ    o_5xx_fpr9,400
    .equ    o_5xx_fpr10,404
    .equ    o_5xx_fpr11,408
    .equ    o_5xx_fpr12,412
    .equ    o_5xx_fpr13,416
    .equ    o_5xx_fpr14,420
    .equ    o_5xx_fpr15,424
    .equ    o_5xx_fpr16,428
    .equ    o_5xx_fpr17,432
    .equ    o_5xx_fpr18,436
    .equ    o_5xx_fpr19,440
    .equ    o_5xx_fpr20,444
    .equ    o_5xx_fpr21,448
    .equ    o_5xx_fpr22,452
    .equ    o_5xx_fpr23,456
    .equ    o_5xx_fpr24,460
    .equ    o_5xx_fpr25,464
    .equ    o_5xx_fpr26,468
    .equ    o_5xx_fpr27,472
    .equ    o_5xx_fpr28,476
    .equ    o_5xx_fpr29,480
    .equ    o_5xx_fpr30,484
    .equ    o_5xx_fpr31,488
    
    
    #
    # PowerPC Special Purpose Register numbers
    # (table 3-3 in 565 um)

    .equ    spr_xer,1                   
    .equ    spr_lr,8                        
    .equ    spr_ctr,9                   
    .equ    spr_dsisr,18                    
    .equ    spr_dar,19                  
    .equ    spr_dec,22                  
    .equ    spr_srr0,26                 
    .equ    spr_srr1,27                 
    .equ    spr_tbl,268     # 284 for write only
    .equ    spr_tbu,269     # 285 for write only
    .equ    spr_sprg0,272               
    .equ    spr_sprg1,273               
    .equ    spr_sprg2,274               
    .equ    spr_sprg3,275               
    .equ    spr_pvr,287                 
    .equ    spr_5xx_eie,80              
    .equ    spr_5xx_eid,81              
    .equ    spr_5xx_nri,82              
    .equ    spr_5xx_cmpa,144            
    .equ    spr_5xx_cmpb,145            
    .equ    spr_5xx_cmpc,146            
    .equ    spr_5xx_cmpd,147            
    .equ    spr_5xx_ecr,148
    .equ    spr_5xx_der,149             
    .equ    spr_5xx_counta,150          
    .equ    spr_5xx_countb,151          
    .equ    spr_5xx_cmpe,152            
    .equ    spr_5xx_cmpf,153            
    .equ    spr_5xx_cmpg,154            
    .equ    spr_5xx_cmph,155            
    .equ    spr_5xx_lctrl1,156          
    .equ    spr_5xx_lctrl2,157          
    .equ    spr_5xx_ictrl,158           
    .equ    spr_5xx_bar,159             
    .equ    spr_5xx_dpdr,630            
    .equ    spr_5xx_immr,638            
    .equ    spr_5xx_ic_bbcmcr,560
    .equ    spr_5xx_l2umcr,568
    .equ    spr_5xx_mi_rba0,784
    .equ    spr_5xx_mi_rba1,785
    .equ    spr_5xx_mi_rba2,786
    .equ    spr_5xx_mi_rba3,787
    .equ    spr_5xx_mi_ra0,816
    .equ    spr_5xx_mi_ra1,817      
    .equ    spr_5xx_mi_ra2,818
    .equ    spr_5xx_mi_ra3,819
    .equ    spr_5xx_l2u_rba0,792
    .equ    spr_5xx_l2u_rba1,793
    .equ    spr_5xx_l2u_rba2,794
    .equ    spr_5xx_l2u_rba3,795
    .equ    spr_5xx_l2u_ra0,824
    .equ    spr_5xx_l2u_ra1,825
    .equ    spr_5xx_l2u_ra2,826
    .equ    spr_5xx_l2u_ra3,827
    .equ    spr_5xx_fpecr,1022


######################################################################

    .text

# This is the entry point upon reset.  The MPC5XX peripherals must be
# initalized properly, beginning with the memory controller, in order for
# the system to start properly.
#
# On the MPC5XX, the part can be configured coming out of power on reset
# by use of a Hard Reset Configuration Word.  This word defines the
# MSR[IP] setting, the boot ROM port size and a few other items.  This
# Config Word is only used if the system asserts RSTCONF_L during
# power-on reset.  If RSTCONF_L is not asserted, then the MPC5XX uses an
# internal default word consisting entirely of zeros.  The Config Word
# looks like (See Chapter 7 of the MPC565 User's Manual):
#
# Bit 0:        EARB - External Arbitration
# Bit 1:        IP - Initial Interrupt Prefix, IP == 0 -> MSR[IP] = 0, IP==1 -> MSR[IP]=1
# Bit 3:        BDIS - Boot Disable, if 1
# Bit 4,5:      BPS - Boot Port Size, 00 == 32bit (default), 01 == 8bit, 10 == 16bit port
# Bit 6:8:      Reserved. Must not be set high.
# Bit 9,10:     DBGC - Debug Pins Config
# Bit 11:       DBPC - Debug Port Pins Config
# Bit 12:       ATWC - Address Type Write Enable Config
# Bit 13,14:    EBDF - External Bus Division Factor
# Bit 15:       Reserved.  Must not be set high.
# Bit 16:       PRPM - Peripheral Mode Enable
# Bit 17,18:    SC - Single Chip Select, 00=extended chip 32 bits data, 01=ext. chip 16 bits data
#                               10=single chip and show cycles, 11=single chip
# Bit 19:       ETRE - Exception Table Relocation Enable
# Bit 20:       FLEN - Flash Enable, 0=flash disabled (boot from external mem), 1=flash enabled
# Bit 21:       EN_COMP - Enable Compression
# Bit 22:       EXC_COMP - Exception Compression
# Bit 23:       Reserved. Must not be set high.
# Bit 24,25:    OERC - Other Exceptions Relocation Control
# Bit 26-27:    Reserved
# Bit 28-30:    ISB - Internal Space Base Select
# Bit 31:       DME - Dual Mapping Enable


    .equ    IMM_SIZE,   0x00400000      # Memory Map is 0x40 0000 bytes long
    .equ    HR_MSR,     0x00001002      # 
    .equ    DER,        0x00000003      # turning off all debug enables
    

asm_startmeup:
    
    # Step 1)  Disable FPU, Enable Big-Endian, Supervisor Mode,
    #          Disable Interrupts, and I- or D- address translation.
    
    mfmsr   r31                 # Read current MSR - IP bit might be set 
    addis   r31,r31,(HR_MSR)@h  # Set the RI and ME bits of the MSR
    ori     r31,r31,(HR_MSR)@l  #  and leave IP bit as it was at Reset
    mtmsr   r31
    isync
    
    lis     r31,(DER)@h
    ori     r31,r31,(DER)@l
    mtspr   149,r31
    isync

    # Step 5)  Determine how we entered Reset processing.

hard_reset:

    # Step 1)  Point R1 to the Dual-Ported RAM to use as stack space
    # until the memory controller is initialized.  Enough space is
    # decremented from top of DPRAM for PPC EABI "back-fill".
    
    lis     r3,(__ISB)@h
    ori     r3,r3,(__ISB)@l
    rlwinm  r2,r3,11,21,31      # shift right 21 bits
    
    ori     r2,r2,0x00000800    # set FLEN bit, and leave the rest alone (including ISB we just set)
    mtspr   spr_5xx_immr,r2     # rewrite IMMR register

    lis     r4,(IMM_SIZE-20)@h
    ori     r4,r4,(IMM_SIZE-20)@l
    add     r1,r3,r4            # re-point r1 into internal SRAM

    # Step 2)  Initialize general MPC5xx control modules out of reset.

    bl      mpc5xx_init

soft_reset:

    # Step 3)  Switch to known good debugger stack space.

    lis     r1,(__SP_INIT-20)@h
    ori     r1,r1,(__SP_INIT-20)@l

    # Step 4)  Execute C entry point -- no return