mpc6xx_lo.s

motorola 针对coldfire 5275 评估板的Dbug bootloader源程序

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######################################################################

#
# These routines perform I/O to memory mapped I/O peripherals.
#
# uint32 cpu_iord_8 (void *addr);
# uint32 cpu_iord_16(void *addr);
# uint32 cpu_iord_32(void *addr);
# void   cpu_iowr_8 (void *addr, uint32 data);
# void   cpu_iowr_16(void *addr, uint32 data);
# void   cpu_iowr_32(void *addr, uint32 data);
#
# Under EABI, addr is in r3, and data is in r4.  Return value also in r3
#
cpu_iord_8:
    eieio
    lbz     r3,0(r3)
    eieio
    blr

cpu_iord_16:
    eieio
    lhz     r3,0(r3)
    eieio
    blr

cpu_iord_32:
    eieio
    lwz     r3,0(r3)
    eieio
    blr

cpu_iowr_8:
    eieio
    stb     r4,0(r3)
    eieio
    blr

cpu_iowr_16:
    eieio
    sth     r4,0(r3)
    eieio
    blr

cpu_iowr_32:
    eieio
    stw     r4,0(r3)
    eieio
    blr

cpu_iord_16r:
    eieio
    lhbrx   r3,0,r3
    eieio
    blr

cpu_iord_32r:
    eieio
    lwbrx   r3,0,r3
    eieio
    blr

cpu_iowd_16r:
    eieio
    sthbrx  r4,0,r3
    eieio
    blr

cpu_iowd_32r:
    eieio
    stwbrx  r4,0,r3
    eieio
    blr


######################################################################

#
# These routines read and write the special purpose registers of the
# MPC6XX.  In general, all writes accept a single 32-bit operand in r3,
# and all reads return a 32-bit operand in r3.  Proper synchronization
# is inserted where appropriate.
#
# C prototypes look like:
#
# void   mpc6xx_wr_XXX (uint32 data);
# uint32 mpc6xx_rd_XXX (void);
#


    #
    # MSR
    #
mpc6xx_wr_msr:
    sync
    mtmsr   r3
    isync
    sync
    blr

mpc6xx_rd_msr:
    mfmsr   r3
    isync
    blr

    #
    # SR0-15
    #
mpc6xx_wr_sr0:
mpc6xx_wr_sr1:
mpc6xx_wr_sr2:
mpc6xx_wr_sr3:
mpc6xx_wr_sr4:
mpc6xx_wr_sr5:
mpc6xx_wr_sr6:
mpc6xx_wr_sr7:
mpc6xx_wr_sr8:
mpc6xx_wr_sr9:
mpc6xx_wr_sr10:
mpc6xx_wr_sr11:
mpc6xx_wr_sr12:
mpc6xx_wr_sr13:
mpc6xx_wr_sr14:
mpc6xx_wr_sr15:
    sync
    mtsr    sr0,r3
    sync
    blr

mpc6xx_rd_sr0:
mpc6xx_rd_sr1:
mpc6xx_rd_sr2:
mpc6xx_rd_sr3:
mpc6xx_rd_sr4:
mpc6xx_rd_sr5:
mpc6xx_rd_sr6:
mpc6xx_rd_sr7:
mpc6xx_rd_sr8:
mpc6xx_rd_sr9:
mpc6xx_rd_sr10:
mpc6xx_rd_sr11:
mpc6xx_rd_sr12:
mpc6xx_rd_sr13:
mpc6xx_rd_sr14:
mpc6xx_rd_sr15:
    sync
    mfsr    r3,sr0
    blr

    #
    # TBL
    #
mpc6xx_wr_tbl:
    mtspr   284,r3
    blr

mpc6xx_wr_tbu:
    mtspr   285,r3
    blr

    #
    # TBU
    #
mpc6xx_rd_tbl:
    mftb    r3,268
    blr

mpc6xx_rd_tbu:
    mftb    r3,269
    blr

    #
    # PVR
    #
mpc6xx_rd_pvr:
    mfspr   r3,spr_pvr
    blr

    #
    # IBAT0
    #
mpc6xx_wr_ibat0u:
    sync
    mtspr   spr_ibat0u,r3
    isync
    blr

mpc6xx_rd_ibat0u:
    mfspr   r3,spr_ibat0u
    blr

mpc6xx_wr_ibat0l:
    sync
    mtspr   spr_ibat0l,r3
    isync
    blr

mpc6xx_rd_ibat0l:
    mfspr   r3,spr_ibat0l
    blr

    #
    # IBAT1
    #
mpc6xx_wr_ibat1u:
    sync
    mtspr   spr_ibat1u,r3
    isync
    blr

mpc6xx_rd_ibat1u:
    mfspr   r3,spr_ibat1u
    blr

mpc6xx_wr_ibat1l:
    sync
    mtspr   spr_ibat1l,r3
    isync
    blr

mpc6xx_rd_ibat1l:
    mfspr   r3,spr_ibat1l
    blr

    #
    # IBAT2
    #
mpc6xx_wr_ibat2u:
    sync
    mtspr   spr_ibat2u,r3
    isync
    blr

mpc6xx_rd_ibat2u:
    mfspr   r3,spr_ibat2u
    blr

mpc6xx_wr_ibat2l:
    sync
    mtspr   spr_ibat2l,r3
    isync
    blr

mpc6xx_rd_ibat2l:
    mfspr   r3,spr_ibat2l
    blr

    #
    # IBAT3
    #
mpc6xx_wr_ibat3u:
    sync
    mtspr   spr_ibat3u,r3
    isync
    blr

mpc6xx_rd_ibat3u:
    mfspr   r3,spr_ibat3u
    blr

mpc6xx_wr_ibat3l:
    sync
    mtspr   spr_ibat3l,r3
    isync
    blr

mpc6xx_rd_ibat3l:
    mfspr   r3,spr_ibat3l
    blr

    #
    # DBAT0
    #
mpc6xx_wr_dbat0u:
    sync
    mtspr   spr_dbat0u,r3
    isync
    blr

mpc6xx_rd_dbat0u:
    mfspr   r3,spr_dbat0u
    blr

mpc6xx_wr_dbat0l:
    sync
    mtspr   spr_dbat0l,r3
    isync
    blr

mpc6xx_rd_dbat0l:
    mfspr   r3,spr_dbat0l
    blr

    #
    # DBAT1
    #
mpc6xx_wr_dbat1u:
    sync
    mtspr   spr_dbat1u,r3
    isync
    blr

mpc6xx_rd_dbat1u:
    mfspr   r3,spr_dbat1u
    blr

mpc6xx_wr_dbat1l:
    sync
    mtspr   spr_dbat1l,r3
    isync
    blr

mpc6xx_rd_dbat1l:
    mfspr   r3,spr_dbat1l
    blr

    #
    # DBAT2
    #
mpc6xx_wr_dbat2u:
    sync
    mtspr   spr_dbat2u,r3
    isync
    blr

mpc6xx_rd_dbat2u:
    mfspr   r3,spr_dbat2u
    blr

mpc6xx_wr_dbat2l:
    sync
    mtspr   spr_dbat2l,r3
    isync
    blr

mpc6xx_rd_dbat2l:
    mfspr   r3,spr_dbat2l
    blr

    #
    # DBAT3
    #
mpc6xx_wr_dbat3u:
    sync
    mtspr   spr_dbat3u,r3
    isync
    blr

mpc6xx_rd_dbat3u:
    mfspr   r3,spr_dbat3u
    blr

mpc6xx_wr_dbat3l:
    sync
    mtspr   spr_dbat3l,r3
    isync
    blr

mpc6xx_rd_dbat3l:
    mfspr   r3,spr_dbat3l
    blr

    #
    # SDR1
    #
mpc6xx_wr_sdr1:
    sync
    mtspr   spr_sdr1,r3
    isync
    blr

mpc6xx_rd_sdr1:
    mfspr   r3,spr_sdr1
    blr

    #
    # DAR
    #
mpc6xx_wr_dar:
    sync
    mtspr   spr_dar,r3
    isync
    blr

mpc6xx_rd_dar:
    mfspr   r3,spr_dar
    blr

    #
    # DSISR
    #
mpc6xx_wr_dsisr:
    sync
    mtspr   spr_dsisr,r3
    isync
    blr

mpc6xx_rd_dsisr:
    mfspr   r3,spr_dsisr
    blr

    #
    # DEC
    #
mpc6xx_wr_dec:
    sync
    mtspr   spr_dec,r3
    isync
    blr

mpc6xx_rd_dec:
    mfspr   r3,spr_dec
    blr


    #
    # MPC60x HID0
    #
mpc603_wr_hid0:
mpc603e_wr_hid0:
mpc604_wr_hid0:
mpc604e_wr_hid0:
mpc750_wr_hid0:
    sync
    mtspr   spr_603_hid0,r3
    isync
    sync
    blr

mpc603_rd_hid0:
mpc603e_rd_hid0:
mpc604_rd_hid0:
mpc604e_rd_hid0:
mpc750_rd_hid0:
    mfspr   r3,spr_603_hid0
    blr

    #
    # MPC603 DMISS
    #
mpc603_wr_dmiss:
mpc603e_wr_dmiss:
    mtspr   spr_603_dmiss,r3
    isync
    sync
    blr

mpc603_rd_dmiss:
mpc603e_rd_dmiss:
    mfspr   r3,spr_603_dmiss
    blr

    #
    # MPC603 DCMP
    #
mpc603_wr_dcmp:
mpc603e_wr_dcmp:
    mtspr   spr_603_dcmp,r3
    isync
    sync
    blr

mpc603_rd_dcmp:
mpc603e_rd_dcmp:
    mfspr   r3,spr_603_dcmp
    blr

    #
    # MPC603 HASH1
    #
mpc603_rd_hash1:
mpc603e_rd_hash1:
    mfspr   r3,spr_603_hash1
    blr

    #
    # MPC603 HASH2
    #
mpc603_rd_hash2:
mpc603e_rd_hash2:
    mfspr   r3,spr_603_hash2
    blr

    #
    # MPC603 IMISS
    #
mpc603_wr_imiss:
mpc603e_wr_imiss:
    mfspr   r3,spr_603_imiss
    blr

mpc603_rd_imiss:
mpc603e_rd_imiss:
    mfspr   r3,spr_603_imiss
    blr

    #
    # MPC603 ICMP
    #
mpc603_wr_icmp:
mpc603e_wr_icmp:
    mtspr   spr_603_icmp,r3
    isync
    sync
    blr

mpc603e_rd_icmp: