📄 mpc6xx_lo.s
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.equ spr_603e_imiss,980
.equ spr_603e_icmp,981
.equ spr_603e_rpa,982
.equ spr_603e_iabr,1010
.equ spr_603e_ear,282
.equ spr_604_hid0,1008
.equ spr_604_pmc1,953
.equ spr_604_pmc2,954
.equ spr_604_mmcr0,952
.equ spr_604_sda,959
.equ spr_604_sia,955
.equ spr_604_iabr,1010
.equ spr_604_dabr,1013
.equ spr_604_ear,282
.equ spr_604_pir,1023
.equ spr_604e_hid0,1008
.equ spr_604e_hid1,1009
.equ spr_604e_pmc1,953
.equ spr_604e_pmc2,954
.equ spr_604e_pmc3,957
.equ spr_604e_pmc4,958
.equ spr_604e_mmcr0,952
.equ spr_604e_mmcr1,956
.equ spr_604e_sda,959
.equ spr_604e_sia,955
.equ spr_604e_iabr,1010
.equ spr_604e_dabr,1013
.equ spr_604e_ear,282
.equ spr_604e_pir,1023
.equ spr_750_upmc1,937
.equ spr_750_upmc2,938
.equ spr_750_upmc3,941
.equ spr_750_upmc4,942
.equ spr_750_usia,939
.equ spr_750_ummcr0,936
.equ spr_750_ummcr1,940
.equ spr_750_hid0,1008
.equ spr_750_hid1,1009
.equ spr_750_pmc1,953
.equ spr_750_pmc2,954
.equ spr_750_pmc3,957
.equ spr_750_pmc4,958
.equ spr_750_mmcr0,952
.equ spr_750_mmcr1,956
.equ spr_750_sia,955
.equ spr_750_thrm1,1020
.equ spr_750_thrm2,1021
.equ spr_750_thrm3,1022
.equ spr_750_ictc,1019
.equ spr_750_l2cr,1017
.equ spr_750_iabr,1010
.equ spr_750_dabr,1013
.equ spr_750_ear,282
######################################################################
######################################################################
######################################################################
.text
#
# This is the entry point upon reset, or the RESET command. This
# code assumes that _NO_DRAM_IS_PRESENT_!!!! This code assumes that
# a memory controller will need software initialization.
#
asm_startmeup:
# Step 1) Disable FPU, Enable Big-Endian, Supervisor Mode,
# Disable Interrupts, and I- or D- address translation.
#
.equ HR_MSR,0x00001002
addis r31,r0,(HR_MSR)@h
ori r31,r31,(HR_MSR)@l
mtmsr r31
isync
# Step 2) Invalidate the Instruction and Data caches, d-cache disabled
# Machine check pin enabled HID0[EMCP].
#
# MPC602, MPC603, MPC603e, MPC604, MPC604e all have HID0 as
# spr1008, and all have HID0[EMCP,ICFI,DCFI] in the same
# bit locations
#
.equ HR_HID0_a,0x00000C00
.equ HR_HID0_b,0x80000000
addis r31,r0,(HR_HID0_a)@h
ori r31,r31,(HR_HID0_a)@l
addis r30,r0,(HR_HID0_b)@h
ori r30,r30,(HR_HID0_b)@l
sync
mtspr spr_603_hid0,r31 # set invalidate bits
mtspr spr_603_hid0,r30 # clear invalidate bits
isync
# Step 3) Clear out the TLBs.
#
# MPC602, MPC603, MPC603e, MPC604, MPC604e all accept the TLBIE
# instruction.
#
# 128 iterations is sufficient for all current parts, and perhaps
# a few newer ones?
#
addi r0,0,1
addi r3,0,0
addi r4,0,0
sync
tlbloop:
tlbie r4
tlbsync
addi r4,r4,0x1000
add. r3,r3,r0
cmpli cr0,0,r3,128
bne tlbloop
addis r30,0,0 # Zero r30
mtcrf 0xFF,r30 # Clear out CRs
# Step 4) Zero FPU registers
#
b init_fpu
zero_for_fpu:
#dc.l 0
.long 0
init_fpu:
addis r28,0,(zero_for_fpu)@h
ori r28,r28,(zero_for_fpu)@l
mfmsr r4
isync
addi r3,r4,0x2000 # MSR[FP]=1
mtmsr r3
sync
lfd f0,0(r28)
lfd f1,0(r28)
lfd f2,0(r28)
lfd f3,0(r28)
lfd f4,0(r28)
lfd f5,0(r28)
lfd f6,0(r28)
lfd f7,0(r28)
lfd f8,0(r28)
lfd f9,0(r28)
lfd f10,0(r28)
lfd f11,0(r28)
lfd f12,0(r28)
lfd f13,0(r28)
lfd f14,0(r28)
lfd f15,0(r28)
lfd f16,0(r28)
lfd f17,0(r28)
lfd f18,0(r28)
lfd f19,0(r28)
lfd f20,0(r28)
lfd f21,0(r28)
lfd f22,0(r28)
lfd f23,0(r28)
lfd f24,0(r28)
lfd f25,0(r28)
lfd f26,0(r28)
lfd f27,0(r28)
lfd f28,0(r28)
lfd f29,0(r28)
lfd f30,0(r28)
lfd f31,0(r28)
mtfsfi 0,0
mtfsfi 1,0
mtfsfi 2,0
mtfsfi 3,0
mtfsfi 4,0
mtfsfi 5,0
mtfsfi 6,0
mtfsfi 7,0
isync
mtmsr r4 # MSR[FP]=0
sync
# Step 5) Provide default settings special purpose registers
#
mtspr spr_xer,r30 # spr1
mtspr spr_ctr,r30 # spr9
mtspr 284,r30 # tbl
mtspr 285,r30 # tbu
mtspr 284,r30 # tbl
isync
mtspr spr_ibat0u,r30 # spr528
mtspr spr_ibat0l,r30 # spr529
mtspr spr_ibat1u,r30 # spr530
mtspr spr_ibat1l,r30 # spr531
mtspr spr_ibat2u,r30 # spr532
mtspr spr_ibat2l,r30 # spr533
mtspr spr_ibat3u,r30 # spr534
mtspr spr_ibat3l,r30 # spr535
mtspr spr_dbat0u,r30 # spr536
mtspr spr_dbat0l,r30 # spr537
mtspr spr_dbat1u,r30 # spr538
mtspr spr_dbat1l,r30 # spr539
mtspr spr_dbat2u,r30 # spr540
mtspr spr_dbat2l,r30 # spr541
mtspr spr_dbat3u,r30 # spr542
mtspr spr_dbat3l,r30 # spr543
isync
mtsr sr0,r30 # Clear out Segment Registers
mtsr sr1,r30
mtsr sr2,r30
mtsr sr3,r30
mtsr sr4,r30
mtsr sr5,r30
mtsr sr6,r30
mtsr sr7,r30
mtsr sr8,r30
mtsr sr9,r30
mtsr sr10,r30
mtsr sr11,r30
mtsr sr12,r30
mtsr sr13,r30
mtsr sr14,r30
mtsr sr15,r30
isync
mtspr spr_sdr1,r30 # spr25
# mtspr spr_dar,r30 # spr19
# mtspr spr_dsisr,r30 # spr18
mtspr spr_srr0,r30 # spr26
mtspr spr_srr1,r30 # spr27
mtspr spr_sprg0,r30 # spr272
mtspr spr_sprg1,r30 # spr273
mtspr spr_sprg2,r30 # spr274
mtspr spr_sprg3,r30 # spr275
# Step 6) Provide default settings processor specific registers
#
mfspr r3,spr_pvr
rlwinm r3,r3,16,16,31
cmpli cr0,0,r3,PVR_602
bc 12,2,init_spr_602 # beq
cmpli cr0,0,r3,PVR_603
bc 12,2,init_spr_603 # beq
cmpli cr0,0,r3,PVR_603E
bc 12,2,init_spr_603E # beq
cmpli cr0,0,r3,PVR_603EV
bc 12,2,init_spr_603EV # beq
cmpli cr0,0,r3,PVR_604
bc 12,2,init_spr_604 # beq
cmpli cr0,0,r3,PVR_604E
bc 12,2,init_spr_604E # beq
cmpli cr0,0,r3,PVR_MACH5
bc 12,2,init_spr_604E # beq
cmpli cr0,0,r3,PVR_750
bc 12,2,init_spr_750 # beq
b init_spr_done
init_spr_602:
b init_spr_done
init_spr_603:
init_spr_603E:
init_spr_603EV:
mtspr spr_603_dmiss,r30
mtspr spr_603_dcmp,r30
mtspr spr_603_imiss,r30
mtspr spr_603_icmp,r30
mtspr spr_603_rpa,r30
mtspr spr_603_iabr,r30
mtspr spr_603_ear,r30
b init_spr_done
init_spr_604:
# mtspr spr_604_pmc1,r30
# mtspr spr_604_pmc2,r30
mtspr spr_604_mmcr0,r30
mtspr spr_604_iabr,r30
mtspr spr_604_ear,r30
mfspr r3,spr_604_hid0
ori r3,r3,0x0080 # HID0[SIED]
mtspr spr_604_hid0,r3
isync
b init_spr_done
init_spr_604E:
init_spr_MACH5:
# mtspr spr_604e_pmc1,r30
# mtspr spr_604e_pmc2,r30
# mtspr spr_604e_pmc3,r30
# mtspr spr_604e_pmc4,r30
mtspr spr_604e_mmcr0,r30
mtspr spr_604e_mmcr1,r30
mtspr spr_604e_iabr,r30
# mtspr spr_604e_ear,r30
mfspr r3,spr_604e_hid0
ori r3,r3,0x0080 # HID0[SIED]
mtspr spr_604e_hid0,r3
isync
b init_spr_done
init_spr_750:
# mtspr spr_750_pmc1,r30
# mtspr spr_750_pmc2,r30
# mtspr spr_750_pmc3,r30
# mtspr spr_750_pmc4,r30
mtspr spr_750_mmcr0,r30
mtspr spr_750_mmcr1,r30
# mtspr spr_750_thrm1,r30
# mtspr spr_750_thrm2,r30
# mtspr spr_750_thrm3,r30
mtspr spr_750_ictc,r30
addis r29,0,0x0020
sync
mtspr spr_750_l2cr,r30 # L2CR[L2E]=0
sync
mtspr spr_750_l2cr,r29 # L2CR[L2I]=1
addi r29,0,0x0001
l2loop:
mfspr r28,spr_750_l2cr
cmpw r28,r29 # L2CR[L2IP]
beq l2loop
sync
mtspr spr_750_l2cr,r30 # L2CR[L2I]=0
sync
mtspr spr_750_iabr,r30
mtspr spr_750_dabr,r30
# mtspr spr_750_ear,r30
b init_spr_done
init_spr_done:
sync
isync
# Step 7) Initialize memory controller.
#
bl mpc10x_init
# Step 8) Switch to known good debugger stack space. Memory
# controller initialization had better be successful!!!
#
addis r1,r0,(__SP_INIT-20)@h
ori r1,r1,(__SP_INIT-20)@l
# Step 9) Execute C entry point -- no return
#
addis r3,r0,(main)@h
ori r3,r3,(main)@l
mtspr LR,r3
blr # branch to C main()
######################################################################
#
# When this function is invoked from the exception handler headers
# above, the following is true:
#
# sprg0 == r31
# sprg1 == LR
# LR[16-23] == exception number
#
# This routine then saves the entire context and invokes the C
# exception handler.
#
# At an exception, address and data translation are turned off
# MSR[IR,DR] = 0,0.
#
.equ MSR_E_MASK,0x87C0FFFF
asm_exception_body:
# Point r31 to the user register data structure
addis r31,r0,(context)@h
ori r31,r31,(context)@l
# Store all GPRs.
stw r0,o_r0(r31) # store r0
stw r1,o_r1(r31) # store r1
stw r2,o_r2(r31) # store r2
stw r3,o_r3(r31) # store r3
stw r4,o_r4(r31) # store r4
stw r5,o_r5(r31) # store r5
stw r6,o_r6(r31) # store r6
stw r7,o_r7(r31) # store r7
stw r8,o_r8(r31) # store r8
stw r9,o_r9(r31) # store r9
stw r10,o_r10(r31) # store r10
stw r11,o_r11(r31) # store r11
stw r12,o_r12(r31) # store r12
stw r13,o_r13(r31) # store r13
stw r14,o_r14(r31) # store r14
stw r15,o_r15(r31) # store r15
stw r16,o_r16(r31) # store r16
stw r17,o_r17(r31) # store r17
stw r18,o_r18(r31) # store r18
stw r19,o_r19(r31) # store r19
stw r20,o_r20(r31) # store r20
stw r21,o_r21(r31) # store r21
stw r22,o_r22(r31) # store r22
stw r23,o_r23(r31) # store r23
stw r24,o_r24(r31) # store r24
stw r25,o_r25(r31) # store r25
stw r26,o_r26(r31) # store r26
stw r27,o_r27(r31) # store r27
stw r28,o_r28(r31) # store r28
stw r29,o_r29(r31) # store r29
stw r30,o_r30(r31) # store r30
mfspr r10,spr_sprg0 # r31 at exception (asm_exception_head)
stw r10,o_r31(r31) # store r31
sync
isync
# mfcr r11
# stw r11,o_cr(r31)
# sync
# Zero r0
addis r0,0,0
# Reconstruct MSR -- !!! Do I really want to reconstruct???
addis r10,r0,(MSR_E_MASK)@h
ori r10,r10,(MSR_E_MASK)@l
mfspr r11,spr_srr1
and r11,r10,r11
addis r12,r0,(~MSR_E_MASK)@h
ori r12,r12,(~MSR_E_MASK)@l
mfmsr r13
isync
and r13,r12,r13
or r10,r11,r13
# Save MSR, CR, IP, XER, LR, CTR
mfcr r11
mfspr r12,spr_srr0
mfspr r13,spr_xer
mfspr r14,spr_sprg1 # lr at exception (asm_exception_head)
mfspr r15,spr_ctr
stw r10,o_msr(r31)
stw r11,o_cr(r31)
stw r12,o_srr0(r31)
stw r13,o_xer(r31)
stw r14,o_lr(r31)
stw r15,o_ctr(r31)
sync
# Save LR before calling routines (LR contains exception number)
# (Once LR saved, it is okay to use subroutine calls)
#
mfspr r30,spr_lr
mtspr spr_sprg1,r30 # LR from bl in asm_exception_head
#
# Change the MSR to suit the needs ot the debugger.
# No interrupts, tracing, address or data translations.
#
.equ DBUG_MSR,0x00001002
addis r30,r0,(DBUG_MSR)@h
ori r30,r30,(DBUG_MSR)@l
mtmsr r30
isync
# Store Floating Point registers
mfmsr r4
isync
addi r3,r4,0x2000 # MSR[FP]=1
mtmsr r3
sync
stfd f0,o_f0(r31)
mffs f0
stfd f0,o_fpscr(r31)
stfd f1,o_f1(r31)
stfd f2,o_f2(r31)
stfd f3,o_f3(r31)
stfd f4,o_f4(r31)
stfd f5,o_f5(r31)
stfd f6,o_f6(r31)
stfd f7,o_f7(r31)
stfd f8,o_f8(r31)
stfd f9,o_f9(r31)
stfd f10,o_f10(r31)
stfd f11,o_f11(r31)
stfd f12,o_f12(r31)
stfd f13,o_f13(r31)
stfd f14,o_f14(r31)
stfd f15,o_f15(r31)
stfd f16,o_f16(r31)
stfd f17,o_f17(r31)
stfd f18,o_f18(r31)
stfd f19,o_f19(r31)
stfd f20,o_f20(r31)
stfd f21,o_f21(r31)
stfd f22,o_f22(r31)
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