📄 mpc6xx_hi.c
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/*
* File: mpc6xx_hi.c
* Purpose: High level MPC6XX specific support routines.
*
* Notes: To add support for another 60X type processor, follow
* these steps.
*
* 1) Edit mpc60x.h and create the C union for the new
* processor specific registers. Make the union name
* reflect the processor name.
*
* 2) Edit mpc60xinc.c and list the new processor specific
* registers just added to mpc60x.h. Make sure the fields
* reflect the new processor name. Compile and regenerate
* the mpc60x.inc assembly include file.
*
* 3) Edit mpc60x_lo.s and add the new processor to the
* init_spr, save_spr, and restore_spr sections in this
* file. Also add the spr utility routines.
*
* 4) Edit mpc60x_hi.c and add the new processor by
* creating a register table for it with the processor
* specific registers in it. Include the new processor
* in the switch statement in cpu_regtab().
*
* 5) #define's for the new processor go in mpc60x.h
* with the processor name as the beginning of the macro.
*
* ie MPC60X_MSR_* is for all 60x type processors, but
* MPC750_HID1_* is for the MPC750 HID1 spr.
*
*/
#include "src/include/dbug.h"
#include "src/uif/cpu.h"
#include "src/uif/bkpt.h"
/********************************************************************/
/*
* This defines the data structure which will hold the values
* of the registers of the user task.
*/
REGISTERS context;
/********************************************************************/
/*
* Strings displayed upon bootup.
*/
#if (defined(CPU_MPC60X) || \
defined(CPU_MPC602) || \
defined(CPU_MPC603) || \
defined(CPU_MPC603E) || \
defined(CPU_MPC604) || \
defined(CPU_MPC604E) || \
defined(CPU_MPC740) || \
defined(CPU_MPC750) )
const char CPU_STR[] = "MPC6XX";
#else
#error "Error: Unsupported MPC6XX CPU!"
#endif
const int CPU_VER_MAJOR = 2;
const char CPU_VER_MINOR = 'a';
/********************************************************************/
/*
* Data structure for managing PowerPC registers. All regs 32-bits.
*/
typedef struct
{
char *reg_name;
uint32 reg_spr;
uint32 volatile *reg_offset;
} ppc_reg;
/*
* Registers common to all 60X processors.
*/
static const ppc_reg ppctab[] =
{
{ "r0", 0, &context.r0 },
{ "r1", 0, &context.r1 },
{ "r2", 0, &context.r2 },
{ "r3", 0, &context.r3 },
{ "r4", 0, &context.r4 },
{ "r5", 0, &context.r5 },
{ "r6", 0, &context.r6 },
{ "r7", 0, &context.r7 },
{ "r8", 0, &context.r8 },
{ "r9", 0, &context.r9 },
{ "r10", 0, &context.r10 },
{ "r11", 0, &context.r11 },
{ "r12", 0, &context.r12 },
{ "r13", 0, &context.r13 },
{ "r14", 0, &context.r14 },
{ "r15", 0, &context.r15 },
{ "r16", 0, &context.r16 },
{ "r17", 0, &context.r17 },
{ "r18", 0, &context.r18 },
{ "r19", 0, &context.r19 },
{ "r20", 0, &context.r20 },
{ "r21", 0, &context.r21 },
{ "r22", 0, &context.r22 },
{ "r23", 0, &context.r23 },
{ "r24", 0, &context.r24 },
{ "r25", 0, &context.r25 },
{ "r26", 0, &context.r26 },
{ "r27", 0, &context.r27 },
{ "r28", 0, &context.r28 },
{ "r29", 0, &context.r29 },
{ "r30", 0, &context.r30 },
{ "r31", 0, &context.r31 },
{ "f0", 0, &context.f0 },
{ "f1", 0, &context.f1 },
{ "f2", 0, &context.f2 },
{ "f3", 0, &context.f3 },
{ "f4", 0, &context.f4 },
{ "f5", 0, &context.f5 },
{ "f6", 0, &context.f6 },
{ "f7", 0, &context.f7 },
{ "f8", 0, &context.f8 },
{ "f9", 0, &context.f9 },
{ "f10", 0, &context.f10 },
{ "f11", 0, &context.f11 },
{ "f12", 0, &context.f12 },
{ "f13", 0, &context.f13 },
{ "f14", 0, &context.f14 },
{ "f15", 0, &context.f15 },
{ "f16", 0, &context.f16 },
{ "f17", 0, &context.f17 },
{ "f18", 0, &context.f18 },
{ "f19", 0, &context.f19 },
{ "f20", 0, &context.f20 },
{ "f21", 0, &context.f21 },
{ "f22", 0, &context.f22 },
{ "f23", 0, &context.f23 },
{ "f24", 0, &context.f24 },
{ "f25", 0, &context.f25 },
{ "f26", 0, &context.f26 },
{ "f27", 0, &context.f27 },
{ "f28", 0, &context.f28 },
{ "f29", 0, &context.f29 },
{ "f30", 0, &context.f30 },
{ "f31", 0, &context.f31 },
{ "cr", 0, &context.cr },
{ "fpscr", 0, &context.fpscr },
{ "XER", 1, &context.xer },
{ "LR", 8, &context.lr },
{ "CTR", 9, &context.ctr },
{ "TBU", 268, &context.tbu },
{ "TBL", 269, &context.tbl },
{ "msr", 0, &context.msr },
{ "PVR", 287, &context.pvr },
{ "IBAT0U", 528, &context.ibat0u },
{ "IBAT0L", 529, &context.ibat0l },
{ "IBAT1U", 530, &context.ibat1u },
{ "IBAT1L", 531, &context.ibat1l },
{ "IBAT2U", 532, &context.ibat2u },
{ "IBAT2L", 533, &context.ibat2l },
{ "IBAT3U", 534, &context.ibat3u },
{ "IBAT3L", 535, &context.ibat3l },
{ "DBAT0U", 536, &context.dbat0u },
{ "DBAT0L", 537, &context.dbat0l },
{ "DBAT1U", 538, &context.dbat1u },
{ "DBAT1L", 539, &context.dbat1l },
{ "DBAT2U", 540, &context.dbat2u },
{ "DBAT2L", 541, &context.dbat2l },
{ "DBAT3U", 542, &context.dbat3u },
{ "DBAT3L", 543, &context.dbat3l },
{ "sr0", 0, &context.sr0 },
{ "sr1", 0, &context.sr1 },
{ "sr2", 0, &context.sr2 },
{ "sr3", 0, &context.sr3 },
{ "sr4", 0, &context.sr4 },
{ "sr5", 0, &context.sr5 },
{ "sr6", 0, &context.sr6 },
{ "sr7", 0, &context.sr7 },
{ "sr8", 0, &context.sr8 },
{ "sr9", 0, &context.sr9 },
{ "sr10", 0, &context.sr10 },
{ "sr11", 0, &context.sr11 },
{ "sr12", 0, &context.sr12 },
{ "sr13", 0, &context.sr13 },
{ "sr14", 0, &context.sr14 },
{ "sr15", 0, &context.sr15 },
{ "SDR1", 25, &context.sdr1 },
{ "DAR", 19, &context.dar },
{ "DSISR", 18, &context.dsisr },
{ "SRR0", 26, &context.srr0 },
{ "SRR1", 27, &context.srr1 },
{ "SPRG0", 272, &context.sprg0 },
{ "SPRG1", 273, &context.sprg1 },
{ "SPRG2", 274, &context.sprg2 },
{ "SPRG3", 275, &context.sprg3 },
{ "DEC", 22, &context.dec },
{ "ip", 0, &context.srr0 },
{ "pc", 0, &context.srr0 },
} ;
/*
* Registers specfic to the MPC602
*/
static const ppc_reg mpc602tab[] =
{
{ "HID0", 1008, &context.psr.mpc602.hid0 },
{ "HID1", 1009, &context.psr.mpc602.hid1 },
{ "DMISS", 976, &context.psr.mpc602.dmiss },
{ "DCMP", 977, &context.psr.mpc602.dcmp },
{ "HASH1", 978, &context.psr.mpc602.hash1 },
{ "HASH2", 979, &context.psr.mpc602.hash2 },
{ "IMISS", 980, &context.psr.mpc602.imiss },
{ "ICMP", 981, &context.psr.mpc602.icmp },
{ "RPA", 982, &context.psr.mpc602.rpa },
{ "TCR", 984, &context.psr.mpc602.tcr },
{ "IBR", 986, &context.psr.mpc602.ibr },
{ "ESASRR", 987, &context.psr.mpc602.esasrr },
{ "SEBR", 990, &context.psr.mpc602.sebr },
{ "SER", 991, &context.psr.mpc602.ser },
{ "IABR", 1010, &context.psr.mpc602.iabr },
{ "EAR", 282, &context.psr.mpc602.ear },
{ "SP", 1021, &context.psr.mpc602.sp },
{ "LT", 1022, &context.psr.mpc602.lt },
} ;
/*
* Registers specfic to the MPC603
*/
static const ppc_reg mpc603tab[] =
{
{ "HID0", 1008, &context.psr.mpc603.hid0 },
{ "DMISS", 976, &context.psr.mpc603.dmiss },
{ "DCMP", 977, &context.psr.mpc603.dcmp },
{ "HASH1", 978, &context.psr.mpc603.hash1 },
{ "HASH2", 979, &context.psr.mpc603.hash2 },
{ "IMISS", 980, &context.psr.mpc603.imiss },
{ "ICMP", 981, &context.psr.mpc603.icmp },
{ "RPA", 982, &context.psr.mpc603.rpa },
{ "IABR", 1010, &context.psr.mpc603.iabr },
{ "EAR", 282, &context.psr.mpc603.ear },
} ;
/*
* Registers specfic to the MPC603e
*/
static const ppc_reg mpc603etab[] =
{
{ "HID0", 1008, &context.psr.mpc603e.hid0 },
{ "HID1", 1009, &context.psr.mpc603e.hid1 },
{ "DMISS", 976, &context.psr.mpc603e.dmiss },
{ "DCMP", 977, &context.psr.mpc603e.dcmp },
{ "HASH1", 978, &context.psr.mpc603e.hash1 },
{ "HASH2", 979, &context.psr.mpc603e.hash2 },
{ "IMISS", 980, &context.psr.mpc603e.imiss },
{ "ICMP", 981, &context.psr.mpc603e.icmp },
{ "RPA", 982, &context.psr.mpc603e.rpa },
{ "IABR", 1010, &context.psr.mpc603e.iabr },
{ "EAR", 282, &context.psr.mpc603e.ear },
} ;
/*
* Registers specfic to the MPC604
*/
static const ppc_reg mpc604tab[] =
{
{ "HID0", 1008, &context.psr.mpc604.hid0 },
{ "PMC1", 953, &context.psr.mpc604.pmc1 },
{ "PMC2", 954, &context.psr.mpc604.pmc2 },
{ "MMCR0", 952, &context.psr.mpc604.mmcr0 },
{ "SDA", 959, &context.psr.mpc604.sda },
{ "SIA", 955, &context.psr.mpc604.sia },
{ "IABR", 1010, &context.psr.mpc604.iabr },
{ "DABR", 1013, &context.psr.mpc604.dabr },
{ "EAR", 282, &context.psr.mpc604.ear },
{ "PIR", 1023, &context.psr.mpc604.pir },
} ;
/*
* Registers specfic to the MPC604e
*/
static const ppc_reg mpc604etab[] =
{
{ "HID0", 1008, &context.psr.mpc604e.hid0 },
{ "HID1", 1009, &context.psr.mpc604e.hid1 },
{ "PMC1", 953, &context.psr.mpc604e.pmc1 },
{ "PMC2", 954, &context.psr.mpc604e.pmc2 },
{ "PMC3", 957, &context.psr.mpc604e.pmc3 },
{ "PMC4", 958, &context.psr.mpc604e.pmc4 },
{ "MMCR0", 952, &context.psr.mpc604e.mmcr0 },
{ "MMCR1", 956, &context.psr.mpc604e.mmcr1 },
{ "SDA", 959, &context.psr.mpc604e.sda },
{ "SIA", 955, &context.psr.mpc604e.sia },
{ "IABR", 1010, &context.psr.mpc604e.iabr },
{ "DABR", 1013, &context.psr.mpc604e.dabr },
{ "EAR", 282, &context.psr.mpc604e.ear },
{ "PIR", 1023, &context.psr.mpc604e.pir },
} ;
/*
* Registers specfic to the MPC750
*/
static const ppc_reg mpc750tab[] =
{
{ "UPMC1", 937, &context.psr.mpc750.upmc1 },
{ "UPMC2", 938, &context.psr.mpc750.upmc2 },
{ "UPMC3", 941, &context.psr.mpc750.upmc3 },
{ "UPMC4", 942, &context.psr.mpc750.upmc4 },
{ "USIA", 939, &context.psr.mpc750.usia },
{ "UMMCR0", 936, &context.psr.mpc750.ummcr0 },
{ "UMMCR1", 940, &context.psr.mpc750.ummcr1 },
{ "HID0", 1008, &context.psr.mpc750.hid0 },
{ "HID1", 1009, &context.psr.mpc750.hid1 },
{ "PMC1", 953, &context.psr.mpc750.pmc1 },
{ "PMC2", 954, &context.psr.mpc750.pmc2 },
{ "PMC3", 957, &context.psr.mpc750.pmc3 },
{ "PMC4", 958, &context.psr.mpc750.pmc4 },
{ "MMCR0", 952, &context.psr.mpc750.mmcr0 },
{ "MMCR1", 956, &context.psr.mpc750.mmcr1 },
{ "SIA", 955, &context.psr.mpc750.sia },
{ "THRM1", 1020, &context.psr.mpc750.thrm1 },
{ "THRM2", 1021, &context.psr.mpc750.thrm2 },
{ "THRM3", 1022, &context.psr.mpc750.thrm3 },
{ "ICTC", 1019, &context.psr.mpc750.ictc },
{ "L2CR", 1017, &context.psr.mpc750.l2cr },
{ "IABR", 1010, &context.psr.mpc750.iabr },
{ "DABR", 1013, &context.psr.mpc750.dabr },
{ "EAR", 282, &context.psr.mpc750.ear },
} ;
#define REGTAB_SIZE(TABLE) (sizeof(TABLE) / sizeof(ppc_reg))
/********************************************************************/
static const char INVREG[] = "Error: Invalid Register: %s\n";
static const char FMT8REG[] = "%08X %08X %08X %08X %08X %08X %08X %08X\n";
static const char EXCEPT[] = "Exception %04X: %s\n";
/*
* When cpu_handler() returns, it returns one of the two values below.
* A value of EXEC_RFI means resume execution of code. A value of
* EXEC_DBUG means return to the dBUG prompt, no more execution of
* user code.
*/
#define EXEC_RFI 0
#define EXEC_DBUG 1
int
cpu_trace_count;
static ADDRESS
trace_thru;
ADDRESS
cpu_step_over;
/********************************************************************/
void
cpu_init (void)
{
context.srr0 = (ADDRESS)__USER_SPACE;
context.cr = 0;
context.msr = ( 0
| MPC_MSR_EE
| MPC_MSR_ME
| MPC_MSR_RI
) ;
context.dec = ~0;
trace_thru = 0;
cpu_step_over = 0;
cpu_trace_count = 0;
}
/********************************************************************/
static int
cpu_regtab (const ppc_reg **tab, int *tabsize)
{
/*
* This routine examines the PVR register and returns a pointer
* and size to the processor specific register tables. If
* the processor table is located, TRUE is returned, else FALSE.
*/
int retval = TRUE;
switch (mpc6xx_rd_pvr() & MPC_PVR_VER)
{
case MPC_PVR_602:
if (tab != NULL)
{
*tab = mpc602tab;
*tabsize = REGTAB_SIZE(mpc602tab);
}
else
{
printf("MPC602");
}
break;
case MPC_PVR_603:
if (tab != NULL)
{
*tab = mpc603tab;
*tabsize = REGTAB_SIZE(mpc603tab);
}
else
{
printf("MPC603");
}
break;
case MPC_PVR_603E:
if (tab != NULL)
{
*tab = mpc603etab;
*tabsize = REGTAB_SIZE(mpc603etab);
}
else
{
printf("MPC603e");
}
break;
case MPC_PVR_603EV:
if (tab != NULL)
{
*tab = mpc603etab;
*tabsize = REGTAB_SIZE(mpc603etab);
}
else
{
printf("MPC603ev");
}
break;
case MPC_PVR_604:
if (tab != NULL)
{
*tab = mpc604tab;
*tabsize = REGTAB_SIZE(mpc604tab);
}
else
{
printf("MPC604");
}
break;
case MPC_PVR_604E:
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