📄 mpc6xx.h
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/*
* File: dbug/cpu/ppc/mpc6xx/mpc6xx.h
* Purpose: Definitions for MPC6XX dBUG
*
* Notes:
*
*
* Modifications:
*
*/
#ifndef _DBUG_CPU_MPC6XX_H
#define _DBUG_CPU_MPC6XX_H
/***********************************************************************/
/*
* Common MPC6XX definitions for dBUG
*/
#define ADDRESS uint32
#define INSTRUCTION uint32
#define ILLEGAL 0x00000000
#define CPU_WORD_SIZE 32
/*
* Registers data structure used for context saving and restoring.
*/
typedef volatile struct
{
/*
* USER MODEL UISA
*/
/* General Purpose Registers */
uint32 r0, r1, r2, r3, r4, r5, r6, r7;
uint32 r8, r9, r10, r11, r12, r13, r14, r15;
uint32 r16, r17, r18, r19, r20, r21, r22, r23;
uint32 r24, r25, r26, r27, r28, r29, r30, r31;
/* Floating Point Registers */
#if 1
uint32 f0, f0l, f1, f1l, f2, f2l, f3, f3l;
uint32 f4, f4l, f5, f5l, f6, f6l, f7, f7l;
uint32 f8, f8l, f9, f9l, f10, f10l, f11, f11l;
uint32 f12, f12l, f13, f13l, f14, f14l, f15, f15l;
uint32 f16, f16l, f17, f17l, f18, f18l, f19, f19l;
uint32 f20, f20l, f21, f21l, f22, f22l, f23, f23l;
uint32 f24, f24l, f25, f25l, f26, f26l, f27, f27l;
uint32 f28, f28l, f29, f29l, f30, f30l, f31, f31l;
#else
uint32 f0, f1, f2, f3, f4, f5, f6, f7;
uint32 f8, f9, f10, f11, f12, f13, f14, f15;
uint32 f16, f17, f18, f19, f20, f21, f22, f23;
uint32 f24, f25, f26, f27, f28, f29, f30, f31;
#endif
/* Condition Register */
uint32 cr; /* offset 256 */
/* Floating Point Status and Control Register */
uint32 fpscr; /* offset 260 */
/* XER */
uint32 xer; /* spr 1 */ /* offset 264 */
/* Link Register */
uint32 lr; /* spr 8 */ /* offset 268 */
/* Count Register */
uint32 ctr; /* spr 9 */ /* offset 272 */
/*
* USER MODEL VEA
*/
/*
* Time Base Facility
*
* TBL spr268 (read) spr284 (write)
* TBU spr269 (read) spr285 (write)
*/
uint32 tbl;
uint32 tbu;
/*
* SUPERVISOR MODEL OEA
*/
/*
* Configuration Registers
*/
/* Machine Status Register */
uint32 msr;
/* Processor Version Register, spr287 */
uint32 pvr;
/*
* Memory Management Registers
*/
/* Instruction BAT Registers, spr528-spr535 */
uint32 ibat0u;
uint32 ibat0l;
uint32 ibat1u;
uint32 ibat1l;
uint32 ibat2u;
uint32 ibat2l;
uint32 ibat3u;
uint32 ibat3l;
/* Data BAT Registers, spr536-543 */
uint32 dbat0u;
uint32 dbat0l;
uint32 dbat1u;
uint32 dbat1l;
uint32 dbat2u;
uint32 dbat2l;
uint32 dbat3u;
uint32 dbat3l;
/* Segment Registers */
uint32 sr0, sr1, sr2, sr3, sr4, sr5, sr6, sr7;
uint32 sr8, sr9, sr10, sr11, sr12, sr13, sr14, sr15;
/* SDR1, spr25 */
uint32 sdr1;
/*
* Exception Handling Registers
*/
/* Data Address Register, spr19 */
uint32 dar;
/* DSISR, spr18 */
uint32 dsisr;
/* Save and Restore, spr26-spr27 */
uint32 srr0;
uint32 srr1;
/* SPRGs, spr272-spr275 */
uint32 sprg0;
uint32 sprg1;
uint32 sprg2;
uint32 sprg3;
/*
* Miscellaneous Registers
*/
/* Decrementer, spr22 */
uint32 dec;
/*
* Processor Specific Registers
*/
union
{
struct mpc602
{
/* Hardware Implementation Register, spr1008 & spr1009 */
uint32 hid0;
uint32 hid1;
/* Software Table Search Registers, spr976-982 */
uint32 dmiss;
uint32 dcmp;
uint32 hash1;
uint32 hash2;
uint32 imiss;
uint32 icmp;
uint32 rpa;
/* Miscellaneous SPRs */
uint32 tcr;
uint32 ibr;
uint32 esasrr;
uint32 sebr;
uint32 ser;
uint32 iabr;
uint32 ear;
uint32 sp;
uint32 lt;
} mpc602;
struct mpc603
{
/* Hardware Implementation Register, spr1008 */
uint32 hid0;
/* Software Table Search Registers, spr976-982 */
uint32 dmiss;
uint32 dcmp;
uint32 hash1;
uint32 hash2;
uint32 imiss;
uint32 icmp;
uint32 rpa;
/* Instruction Address Breakpoint Register, spr1010 */
uint32 iabr;
/* External Address Register, spr282 */
uint32 ear;
} mpc603;
struct mpc603e
{
/* Hardware Implementation Register, spr1008-spr1009 */
uint32 hid0;
uint32 hid1;
/* Software Table Search Registers, spr976-982 */
uint32 dmiss;
uint32 dcmp;
uint32 hash1;
uint32 hash2;
uint32 imiss;
uint32 icmp;
uint32 rpa;
/* Instruction Address Breakpoint Register, spr1010 */
uint32 iabr;
/* External Address Register, spr282 */
uint32 ear;
} mpc603e;
struct mpc604
{
/* Hardware Implementation Register, spr1008 */
uint32 hid0;
/* Performance Monitor Counters, spr953-spr954 */
uint32 pmc1;
uint32 pmc2;
/* Performance Mode Control Register 0, spr952 */
uint32 mmcr0;
/* Sampled Data/Instruction Address, spr959, spr955 */
uint32 sda;
uint32 sia;
/* Instruction Address Breakpoint Register, spr1010 */
uint32 iabr;
/* Data Address Breakpoint Register, spr1013 */
uint32 dabr;
/* External Address Register, spr282 */
uint32 ear;
/* Processor Identification Register, spr1023 */
uint32 pir;
} mpc604;
struct mpc604e
{
/* Hardware Implementation Register, spr1008-spr1009 */
uint32 hid0;
uint32 hid1;
/* Performance Monitor Counters, spr953,954,957,958 */
uint32 pmc1;
uint32 pmc2;
uint32 pmc3;
uint32 pmc4;
/* Performance Mode Control Register 0, spr952,956 */
uint32 mmcr0;
uint32 mmcr1;
/* Sampled Data/Instruction Address, spr959, spr955 */
uint32 sda;
uint32 sia;
/* Instruction Address Breakpoint Register, spr1010 */
uint32 iabr;
/* Data Address Breakpoint Register, spr1013 */
uint32 dabr;
/* External Address Register, spr282 */
uint32 ear;
/* Processor Identification Register, spr1023 */
uint32 pir;
} mpc604e;
struct mpc750
{
/* Performance Counters, (Read Only), spr937,938,941,942 */
uint32 upmc1;
uint32 upmc2;
uint32 upmc3;
uint32 upmc4;
/* Sampled Instruction Address (Read Only), spr939 */
uint32 usia;
/* Monitor Control, (Read Only), spr936,940 */
uint32 ummcr0;
uint32 ummcr1;
/* Hardware Implementation Register, spr1008-spr1009 */
uint32 hid0;
uint32 hid1;
/* Performance Monitor Counters, spr953,954,957,958 */
uint32 pmc1;
uint32 pmc2;
uint32 pmc3;
uint32 pmc4;
/* Performance Mode Control Register 0, spr952,956 */
uint32 mmcr0;
uint32 mmcr1;
/* Sampled Instruction Address, spr955 */
uint32 sia;
/* Thermal Assist Unit Registers, spr1020-spr1022 */
uint32 thrm1;
uint32 thrm2;
uint32 thrm3;
/* Instruction Cache Throttling Control, spr1019 */
uint32 ictc;
/* L2 Control Register, spr1017 */
uint32 l2cr;
/* Instruction Address Breakpoint Register, spr1010 */
uint32 iabr;
/* Data Address Breakpoint Register, spr1013 */
uint32 dabr;
/* External Address Register, spr282 */
uint32 ear;
} mpc750;
} psr;
} REGISTERS;
/***********************************************************************/
/*
* Prototypes for routines invoked by MPC6XX dBUG.
*/
void
asm_switch_context (void *);
void
asm_return_from_call (void);
char *
cpu_get_spr_name (int);
void
mpc6xx_ibr (int, char **);
/***********************************************************************/
#define CPU_CMD_IBR \
{"ibr",3,0,1,0,mpc6xx_ibr, "Instruction Brkpnt", "<addr>"},
#define CPU_CMDS_ALL \
CPU_CMD_IBR
#define CPU_SETCMDS_ALL
/***********************************************************************/
#endif /* _DBUG_CPU_MPC6XX_H */
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