📄 mpc8xx.h
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/*
* File: dbug/cpu/ppc/mpc8xx/mpc8xx.h
* Purpose: Definitions for MPC8XX dBUG
*
* Notes:
*
*
* Modifications:
*
*/
#ifndef _DBUG_CPU_MPC8XX_H
#define _DBUG_CPU_MPC8XX_H
/***********************************************************************/
/*
* Common MPC8XX definitions for dBUG
*/
#define ADDRESS uint32
#define INSTRUCTION uint32
#define ILLEGAL 0x00000000
#define CPU_WORD_SIZE 32
/*
* Registers data structure used for context saving and restoring.
*/
typedef struct
{
uint32 r0, r1, r2, r3, r4, r5, r6, r7;
uint32 r8, r9, r10, r11, r12, r13, r14, r15;
uint32 r16, r17, r18, r19, r20, r21, r22, r23;
uint32 r24, r25, r26, r27, r28, r29, r30, r31;
uint32 cr;
uint32 msr;
uint32 xer, lr, ctr, dsisr, dar, dec;
uint32 srr0, srr1, sprg0, sprg1, sprg2, sprg3;
uint32 tbl, tbu, pvr;
uint32 eie, eid, nri, cmpa, cmpb, cmpc;
uint32 cmpd, icr, der, counta, countb, cmpe;
uint32 cmpf, cmpg, cmph, lctrl1, lctrl2, ictrl;
uint32 bar, dpdr, dpir, immr;
uint32 ic_cst, ic_adr, ic_dat, dc_cst, dc_adr, dc_dat;
uint32 mi_ctr, mi_ap, mi_epn, mi_twc, mi_rpn, mi_dbcam;
uint32 mi_dbram0, mi_dbram1, md_ctr, m_casid, md_ap, md_epn;
uint32 m_twb, md_twc, md_rpn, m_tw, md_dbcam, md_dbram0, md_dbram1;
} REGISTERS;
/*
* Because ANSI C doesn't specify how members of a structure/array are
* stored, use a compiler independent method for accessing the registers.
* The 'registers' data structure is filled in by mpc8xx_lo.s
*/
#define Mpc8xx_reg(OFFSET) \
*(uint32 *)(&((uint8 *)&context)[OFFSET])
#define MPC8XX_R0 0
#define MPC8XX_R1 4
#define MPC8XX_R2 8
#define MPC8XX_R3 12
#define MPC8XX_R4 16
#define MPC8XX_R5 20
#define MPC8XX_R6 24
#define MPC8XX_R7 28
#define MPC8XX_R8 32
#define MPC8XX_R9 36
#define MPC8XX_R10 40
#define MPC8XX_R11 44
#define MPC8XX_R12 48
#define MPC8XX_R13 52
#define MPC8XX_R14 56
#define MPC8XX_R15 60
#define MPC8XX_R16 64
#define MPC8XX_R17 68
#define MPC8XX_R18 72
#define MPC8XX_R19 76
#define MPC8XX_R20 80
#define MPC8XX_R21 84
#define MPC8XX_R22 88
#define MPC8XX_R23 92
#define MPC8XX_R24 96
#define MPC8XX_R25 100
#define MPC8XX_R26 104
#define MPC8XX_R27 108
#define MPC8XX_R28 112
#define MPC8XX_R29 116
#define MPC8XX_R30 120
#define MPC8XX_R31 124
#define MPC8XX_CR 128
#define MPC8XX_MSR 132
#define MPC8XX_XER 136
#define MPC8XX_LR 140
#define MPC8XX_CTR 144
#define MPC8XX_DSISR 148
#define MPC8XX_DAR 152
#define MPC8XX_DEC 156
#define MPC8XX_SRR0 160
#define MPC8XX_SRR1 164
#define MPC8XX_SPRG0 168
#define MPC8XX_SPRG1 172
#define MPC8XX_SPRG2 176
#define MPC8XX_SPRG3 180
#define MPC8XX_TBL 184
#define MPC8XX_TBU 188
#define MPC8XX_PVR 192
#define MPC8XX_EIE 196
#define MPC8XX_EID 200
#define MPC8XX_NRI 204
#define MPC8XX_CMPA 208
#define MPC8XX_CMPB 212
#define MPC8XX_CMPC 216
#define MPC8XX_CMPD 220
#define MPC8XX_ICR 224
#define MPC8XX_DER 228
#define MPC8XX_COUNTA 232
#define MPC8XX_COUNTB 236
#define MPC8XX_CMPE 240
#define MPC8XX_CMPF 244
#define MPC8XX_CMPG 248
#define MPC8XX_CMPH 252
#define MPC8XX_LCTRL1 256
#define MPC8XX_LCTRL2 260
#define MPC8XX_ICTRL 264
#define MPC8XX_BAR 268
#define MPC8XX_DPDR 272
#define MPC8XX_DPIR 276
#define MPC8XX_IMMR 280
#define MPC8XX_IC_CST 284
#define MPC8XX_IC_ADR 288
#define MPC8XX_IC_DAT 292
#define MPC8XX_DC_CST 296
#define MPC8XX_DC_ADR 300
#define MPC8XX_DC_DAT 304
#define MPC8XX_MI_CTR 308
#define MPC8XX_MI_AP 312
#define MPC8XX_MI_EPN 316
#define MPC8XX_MI_TWC 320
#define MPC8XX_MI_RPN 324
#define MPC8XX_MI_DBCAM 328
#define MPC8XX_MI_DBRAM0 332
#define MPC8XX_MI_DBRAM1 336
#define MPC8XX_MD_CTR 340
#define MPC8XX_M_CASID 344
#define MPC8XX_MD_AP 348
#define MPC8XX_MD_EPN 352
#define MPC8XX_M_TWB 356
#define MPC8XX_MD_TWC 360
#define MPC8XX_MD_RPN 364
#define MPC8XX_M_TW 368
#define MPC8XX_MD_DBCAM 372
#define MPC8XX_MD_DBRAM0 376
#define MPC8XX_MD_DBRAM1 380
#define CPU_REG_R0 Mpc8xx_reg(MPC8XX_R0)
#define CPU_REG_R1 Mpc8xx_reg(MPC8XX_R1)
#define CPU_REG_R2 Mpc8xx_reg(MPC8XX_R2)
#define CPU_REG_R3 Mpc8xx_reg(MPC8XX_R3)
#define CPU_REG_R4 Mpc8xx_reg(MPC8XX_R4)
#define CPU_REG_R5 Mpc8xx_reg(MPC8XX_R5)
#define CPU_REG_R6 Mpc8xx_reg(MPC8XX_R6)
#define CPU_REG_R7 Mpc8xx_reg(MPC8XX_R7)
#define CPU_REG_R8 Mpc8xx_reg(MPC8XX_R8)
#define CPU_REG_R9 Mpc8xx_reg(MPC8XX_R9)
#define CPU_REG_R10 Mpc8xx_reg(MPC8XX_R10)
#define CPU_REG_R11 Mpc8xx_reg(MPC8XX_R11)
#define CPU_REG_R12 Mpc8xx_reg(MPC8XX_R12)
#define CPU_REG_R13 Mpc8xx_reg(MPC8XX_R13)
#define CPU_REG_R14 Mpc8xx_reg(MPC8XX_R14)
#define CPU_REG_R15 Mpc8xx_reg(MPC8XX_R15)
#define CPU_REG_R16 Mpc8xx_reg(MPC8XX_R16)
#define CPU_REG_R17 Mpc8xx_reg(MPC8XX_R17)
#define CPU_REG_R18 Mpc8xx_reg(MPC8XX_R18)
#define CPU_REG_R19 Mpc8xx_reg(MPC8XX_R19)
#define CPU_REG_R20 Mpc8xx_reg(MPC8XX_R20)
#define CPU_REG_R21 Mpc8xx_reg(MPC8XX_R21)
#define CPU_REG_R22 Mpc8xx_reg(MPC8XX_R22)
#define CPU_REG_R23 Mpc8xx_reg(MPC8XX_R23)
#define CPU_REG_R24 Mpc8xx_reg(MPC8XX_R24)
#define CPU_REG_R25 Mpc8xx_reg(MPC8XX_R25)
#define CPU_REG_R26 Mpc8xx_reg(MPC8XX_R26)
#define CPU_REG_R27 Mpc8xx_reg(MPC8XX_R27)
#define CPU_REG_R28 Mpc8xx_reg(MPC8XX_R28)
#define CPU_REG_R29 Mpc8xx_reg(MPC8XX_R29)
#define CPU_REG_R30 Mpc8xx_reg(MPC8XX_R30)
#define CPU_REG_R31 Mpc8xx_reg(MPC8XX_R31)
#define CPU_REG_CR Mpc8xx_reg(MPC8XX_CR)
#define CPU_REG_MSR Mpc8xx_reg(MPC8XX_MSR)
#define CPU_REG_XER Mpc8xx_reg(MPC8XX_XER)
#define CPU_REG_LR Mpc8xx_reg(MPC8XX_LR)
#define CPU_REG_CTR Mpc8xx_reg(MPC8XX_CTR)
#define CPU_REG_DSISR Mpc8xx_reg(MPC8XX_DSISR)
#define CPU_REG_DAR Mpc8xx_reg(MPC8XX_DAR)
#define CPU_REG_DEC Mpc8xx_reg(MPC8XX_DEC)
#define CPU_REG_SRR0 Mpc8xx_reg(MPC8XX_SRR0)
#define CPU_REG_SRR1 Mpc8xx_reg(MPC8XX_SRR1)
#define CPU_REG_SPRG0 Mpc8xx_reg(MPC8XX_SPRG0)
#define CPU_REG_SPRG1 Mpc8xx_reg(MPC8XX_SPRG1)
#define CPU_REG_SPRG2 Mpc8xx_reg(MPC8XX_SPRG2)
#define CPU_REG_SPRG3 Mpc8xx_reg(MPC8XX_SPRG3)
#define CPU_REG_TBL Mpc8xx_reg(MPC8XX_TBL)
#define CPU_REG_TBU Mpc8xx_reg(MPC8XX_TBU)
#define CPU_REG_PVR Mpc8xx_reg(MPC8XX_PVR)
#define CPU_REG_EIE Mpc8xx_reg(MPC8XX_EIE)
#define CPU_REG_EID Mpc8xx_reg(MPC8XX_EID)
#define CPU_REG_NRI Mpc8xx_reg(MPC8XX_NRI)
#define CPU_REG_CMPA Mpc8xx_reg(MPC8XX_CMPA)
#define CPU_REG_CMPB Mpc8xx_reg(MPC8XX_CMPB)
#define CPU_REG_CMPC Mpc8xx_reg(MPC8XX_CMPC)
#define CPU_REG_CMPD Mpc8xx_reg(MPC8XX_CMPD)
#define CPU_REG_ICR Mpc8xx_reg(MPC8XX_ICR)
#define CPU_REG_DER Mpc8xx_reg(MPC8XX_DER)
#define CPU_REG_COUNTA Mpc8xx_reg(MPC8XX_COUNTA)
#define CPU_REG_COUNTB Mpc8xx_reg(MPC8XX_COUNTB)
#define CPU_REG_CMPE Mpc8xx_reg(MPC8XX_CMPE)
#define CPU_REG_CMPF Mpc8xx_reg(MPC8XX_CMPF)
#define CPU_REG_CMPG Mpc8xx_reg(MPC8XX_CMPG)
#define CPU_REG_CMPH Mpc8xx_reg(MPC8XX_CMPH)
#define CPU_REG_LCTRL1 Mpc8xx_reg(MPC8XX_LCTRL1)
#define CPU_REG_LCTRL2 Mpc8xx_reg(MPC8XX_LCTRL2)
#define CPU_REG_ICTRL Mpc8xx_reg(MPC8XX_ICTRL)
#define CPU_REG_BAR Mpc8xx_reg(MPC8XX_BAR)
#define CPU_REG_DPDR Mpc8xx_reg(MPC8XX_DPDR)
#define CPU_REG_DPIR Mpc8xx_reg(MPC8XX_DPIR)
#define CPU_REG_IMMR Mpc8xx_reg(MPC8XX_IMMR)
#define CPU_REG_IC_CST Mpc8xx_reg(MPC8XX_IC_CST)
#define CPU_REG_IC_ADR Mpc8xx_reg(MPC8XX_IC_ADR)
#define CPU_REG_IC_DAT Mpc8xx_reg(MPC8XX_IC_DAT)
#define CPU_REG_DC_CST Mpc8xx_reg(MPC8XX_DC_CST)
#define CPU_REG_DC_ADR Mpc8xx_reg(MPC8XX_DC_ADR)
#define CPU_REG_DC_DAT Mpc8xx_reg(MPC8XX_DC_DAT)
#define CPU_REG_MI_CTR Mpc8xx_reg(MPC8XX_MI_CTR)
#define CPU_REG_MI_AP Mpc8xx_reg(MPC8XX_MI_AP)
#define CPU_REG_MI_EPN Mpc8xx_reg(MPC8XX_MI_EPN)
#define CPU_REG_MI_TWC Mpc8xx_reg(MPC8XX_MI_TWC)
#define CPU_REG_MI_RPN Mpc8xx_reg(MPC8XX_MI_RPN)
#define CPU_REG_MI_DBCAM Mpc8xx_reg(MPC8XX_MI_DBCAM)
#define CPU_REG_MI_DBRAM0 Mpc8xx_reg(MPC8XX_MI_DBRAM0)
#define CPU_REG_MI_DBRAM1 Mpc8xx_reg(MPC8XX_MI_DBRAM1)
#define CPU_REG_MD_CTR Mpc8xx_reg(MPC8XX_MD_CTR)
#define CPU_REG_M_CASID Mpc8xx_reg(MPC8XX_M_CASID)
#define CPU_REG_MD_AP Mpc8xx_reg(MPC8XX_MD_AP)
#define CPU_REG_MD_EPN Mpc8xx_reg(MPC8XX_MD_EPN)
#define CPU_REG_M_TWB Mpc8xx_reg(MPC8XX_M_TWB)
#define CPU_REG_MD_TWC Mpc8xx_reg(MPC8XX_MD_TWC)
#define CPU_REG_MD_RPN Mpc8xx_reg(MPC8XX_MD_RPN)
#define CPU_REG_M_TW Mpc8xx_reg(MPC8XX_M_TW)
#define CPU_REG_MD_DBCAM Mpc8xx_reg(MPC8XX_MD_DBCAM)
#define CPU_REG_MD_DBRAM0 Mpc8xx_reg(MPC8XX_MD_DBRAM0)
#define CPU_REG_MD_DBRAM1 Mpc8xx_reg(MPC8XX_MD_DBRAM1)
/***********************************************************************/
/*
* Prototypes for routines invoked by MPC8XX dBUG.
*/
void *
mpc8xx_isb (void);
void
asm_switch_context (void *);
void
asm_return_from_call (void);
void
mpc8xx_rsr_display (void);
char *
cpu_get_spr_name (int);
void
mpc8xx_call (int, char **);
/*
void
mpc8xx_ird (int, char **);
*/
void
mpc8xx_irm (int, char **);
/***********************************************************************/
#define CPU_CMD_CALL \
{"call",4,1,UIF_MAX_ARGS,1,mpc8xx_call, "Call Subroutine", "addr <args>"},
/*
#define CPU_CMD_IRD \
{"ird",3,0,1,0,mpc8xx_ird, "Internal Reg Display", "<module.register>"},
*/
#define CPU_CMD_IMM \
{"imm",3,0,2,0,mpc8xx_irm, "Internal Reg Modify", "module.register data"},
#define CPU_CMDS_ALL \
CPU_CMD_CALL \
CPU_CMD_IMM
#define CPU_SETCMDS_ALL
/***********************************************************************/
#endif /* _DBUG_CPU_MPC8XX_H */
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